Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture

By Parthiv Parta, Vice President, Hardware Engineering, MIPS

November 20, 2024

The rise of opensource RISC-V CPU Instruction Set Architecture (ISA) has led many developers to consider migrating from existing popular computer architectures like x86, Arm, MIPS and more to RISC-V CPU ISA. This transition offers various advantages, including an open-source framework and extensive community support. In this blog, we’ll explore typical migration strategies and considerations from MIPS to RISC-V CPU ISA.

1. Ease of Migration with RISC-V

• Openness of RISC-V: RISC-V is an open standard, allowing for more flexibility and innovation and MIPS has adopted RISC-V in its latest product, including the MIPS P8700.
• Modular Instruction Set Architecture (ISA): RISC-V provides a modular ISA, letting developers choose only the extensions they need.
• Ecosystem: RISC-V boasts a growing ecosystem of tools, software libraries, and community support, which can be beneficial during and after migration.

2. Migrating Software components

To begin the migration process, below are the steps to set up your development environment for RISC-V:

• Toolchain: Install the RISC-V GCC toolchain to compile your code.
• Simulators and Emulators: Use simulators like QEMU or Spike to test your code without needing physical hardware.
• Debugger: Familiarize yourself with debugging tools such as GDB, which is compatible with RISC-V.
• Machine Mode Software: Machine mode software migration from MIPS to RISC-V needs to be considered carefully for the components like bootloader, Supervisor Binary Interface (SBI) and Linux kernels.

3. Code Migration Strategy

3.1 Analyzing the MIPS legacy Codebase

• Functionality: Identify MIPS-specific libraries or hardware dependencies that need replacement with equivalent functionality in RISC-V domain. Analyze existing functionality and map to available RISC-V ISA extensions and possibly look for using vendor specific custom instructions. MIPS provides support for many MIPS legacy instructions as RISC-V custom instructions like translation look aside buffer (TLB) and cache maintenance instructions specific to MIPS CPU TLB and cache Architecture.
• Performance Considerations: Evaluate areas where MIPS-specific optimizations were applied and determine how they can be adapted for RISC-V. MIPS provides RISC-V custom instructions tuned for MIPS CPU pipeline such as Hardware data prefetch to L1 and/or L2 caches.

3.2 Understanding Instruction Set Architecture Differences

MIPS and RISC-V are strikingly similar ISAs. In many cases, the operation and instruction mnemonics of the RISC-V instructions are identical to their MIPS counterparts. Most RISC-V instructions have a direct equivalent in MIPS. RISC-V instruction encodings are different from MIPS encodings. The RISC-V opcode space has been pre-partitioned from the outset in a manner which is intended to be logical and symmetrical. This symmetry aids clean ISA extension design and offers the hope of cheap decoder implementation cost.

• 32b/64b Architecture
  • MIPS ISA provides backward compatibility i.e. 32b code should be able to run on 64b MIPS implementation.
  • 64b RISC-V implementation is not compatible with 32b code, requires 32b specific RISC-V implementation to support.
• Privileged Instructions
  • The RISC-V privileged architecture supports the same functionality as MIPS but is distributed differently among the Control and Status Registers (CSRs). A few significant differences exist. Processor operating modes and transitions are similar between MIPS and RISC-V but not same and has some differences.
  • The RISC-V privileged ISA specification leaves some of details which are specified in the MIPS PRA as implementation dependent. In practice, to design a functioning core and its supporting software, many of those details will need to be specified, for example, caches.
  • There is no static partitioning of virtual address space in RISC-V, . platform-dependent PMA regulates cacheability and other memory attributes.
• Unprivileged Instructions
  • About 95% of baseline RISC-V instructions map to MIPS instructions. Create a mapping table per-extension to simplify the translation process.
  • There are some differences in offset and displacement widths for branch, load, store instructions.
  • There are some differences in floating point, such as rounding modes and NaN handling.
  • RISC-V has more flavors of Atomic Memory Operations (AMO.
• Memory Management (MMU)
  • The physical memory protection extension is similar to the MIPS MPU extension.
  • The RISC-V MMU design does not require a specific software interface with the on-chip cache of the PTEs (a.k.a. the ”TLB”).
• Hardware Virtualization
  • The RISC-V and MIPS Virtualization functions are similar at a high-level and most differences can be eliminated through initialization.
• Interrupt handling
  • Global Interrupt Controller (GIC) functionality is provided through RISC-V Advanced Interrupt Architecture (AIA).
• Debug and Trace
  • RISC-V debug and trace architecture has some differences with similar functionality as MIPS Debug and PDTrace Architecture. To leverage open source, off-the-shelf Debug and Trace tools support, one must migrate fully from MIPS to RISC-V compliant Debug and Trace Architecture.

3.3 Data Structures and Calling Conventions

• Calling Conventions: MIPS and RISC-V have different calling conventions. Make sure to update function signatures and calls accordingly.
• Data Alignment: Review data structures to ensure they align properly in RISC-V, as alignment requirements may differ.

4. Testing and Validation

Basic infrastructure and methods to test and validate MIPS to RISC-V migration are unchanged. ISA specific changes for operating modes, page tables, memory spaces, protection are needed. Random stimuli generation engine needs to update to map instruction, register, modes, configuration databases. Random stimuli generation engine library changes for RISC-V handling of implementation specific structures are needed. RISC-V Instruction Set Simulator will need potential customizations based on implementation. Architecture dependent setup and test macros (test boot code) would need to be changed.

4.1 Unit Testing

Implement unit tests for critical components to ensure functionality remains intact during the migration process.

4.2 System Testing

Conduct system-level tests to validate the complete application’s behavior on RISC-V hardware or emulators.

4.3 Performance Benchmarking

After migration, benchmark your application to identify performance changes. Optimize code where necessary to leverage RISC-V’s strengths.

5. Community and Resources

Leverage the RISC-V community for support during migration:

• Forums and Mailing Lists: Join RISC-V forums and mailing lists for tips and shared experiences from other developers.
• Documentation: The RISC-V Foundation provides extensive documentation that can help you understand the architecture in detail.
• Sample Projects: Look for open-source projects that have already made the transition for inspiration and guidance.

For details on RISC-V , please visit riscv.org

Conclusion

The high similarity between MIPS and RISC-V ISA enables ease of migration from MIPS to RISC-V. Embrace the open-source ethos of RISC-V and leverage its growing ecosystem to build robust and innovative applications.

Share your experience on your next MIPS to RISC-V migration project with the RISC-V community!