Flashback to Basics Friday! Bandwidth...
April 25, 2016
I’ve been thinking for a while (yes, that explains the burning smell) that we should be covering some of the basics of PCI Express here at ExpressYourself in addition to “just” the new stuff. After reading today’s posting, please let me know in the comments whether this is a good idea or not…
One of the questions I’ve been getting a lot recently is along the lines of “How many lanes and of what ‘generation’ of PCI Express do I need?”
This is a fairly straightforward question, and while coming up with a good first-order estimation is also fairly straightforward, it’s not necessarily obvious in the PCI Express specification. Let’s start with the “raw” data rate, which is fairly easy:
To read the full article, click here
Related Semiconductor IP
- PCI Express PHY
- Multi-Channel Flex DMA IP Core for PCI Express
- PCIe - PCI Express Controller
- PCI Express PIPE PHY Transceiver
- Scalable Switch Intel® FPGA IP for PCI Express
Related Blogs
- Flashback to Basics Friday! Bifurcation...
- High Bandwidth Memory Evolution from First Generation HBM to the Latest HBM4
- Black Friday and the Predicted Semiconductor Shortages
- MoSys Fires Up the Bandwidth Engine
Latest Blogs
- Enhancing PCIe6.0 Performance: Flit Sequence Numbers and Selective NAK Explained
- Smarter ASICs and SoCs: Unlocking Real-World Connectivity with eFPGA and Data Converters
- RISC-V Takes First Step Toward International Standardization as ISO/IEC JTC1 Grants PAS Submitter Status
- Running Optimized PyTorch Models on Cadence DSPs with ExecuTorch
- PCIe 6.x: Synopsys IP Selected as First Gold System for Compliance Testing