CCIX Over PCIe: Faster Coherent Interconnects for AI, Networking, 4G/5G, and Storage Designs
Next generation SoC designs require faster coherent interconnects for high performance applications such as machine learning, network processing, storage off-load, in-memory data base and 4G/5G wireless technology. CCIX (Cache Coherent Interconnect for Accelerators), a new protocol standard, provides benefits of cache coherency and peer processing which enables the faster interconnect. CCIX is designed smartly to use the well-established PCIe infrastructure to carry coherency packets across the link with little modification. CCIX specification is compatible with PCIe base specification 4.0. PCIe implementation is extended to implement a CCIX transaction layer, responsible for carrying the coherency messages.
To read the full article, click here
Related Semiconductor IP
- Configurable controllers for PCIe 4.0 and CCIX supporting Dual Mode applications
- Simulation VIP for CCIX
- CCIX 1.0 Verification IP
- CCIX 32G Premium Controller with AMBA bridge II
- CCIX 32G Premium Controller II
Related Blogs
- Cadence Showcases World's First 128GT/s PCIe 7.0 IP Over Optics
- PCIe Over Optical: Transforming High-Speed Data Transmission
- PCIe Verification IP Overview
- Intel’s Atom-based Tunnel Creek SOC with integrated PCIe interface opens new era for embedded developers
Latest Blogs
- Enabling End-to-End EDA Flow on Arm-Based Compute for Infrastructure Flexibility
- Real PPA improvements from analog IC migration
- Design specification: The cornerstone of an ASIC collaboration
- The importance of ADCs in low-power electrocardiography ASICs
- VESA Adaptive-Sync V2 Operation in DisplayPort VIP