Synopsys IP

The functional safety (FuSa) software components in conjunction with Synopsys’ ASIL certified MetaWare Development Tools for Safety and industry leading ARC® FS processors provide comprehensive ASIL compliant solutions which dramatically reduce customers’ risk and SoC certification effort.

The SLM SHS IP is an automated hierarchical test solution for efficiently testing SoCs or designs using multiple IP/cores, including analog/mixed-signal IP, digital logic cores and interface IP.
It significantly reduces test integration time by automatically creating a hierarchical IEEE 1500 network to access and control all IP/cores at the SoC level, and increases test quality of results (QoR), including optimizing test time and power through flexible test scheduling of IP and cores.

The SLM High-Speed Access and Test (HSAT) IP combined with the TestMAX® ALE software uses standard high speed IO interfaces such as PCIe and USB, to get test, debug and monitoring data in and out of an SoC at Gigabit data rates and avoids the need for large numbers of test and interface pins.
Test time can be reduced because the link between the test time and GPIO data rate is eliminated. Further, this solution provides a key component for Synopsys Silicon Lifecycle Management solution allowing manufacturing tests to be repeated in-system and in-field as well as providing high speed access to PVT and functional monitor dat

Proven “Soft” PUF implementation for AMD/Xilinx FPGAs, part of the FPGA configuration file
Offers FPGA users a cryptographic technology to secure their own keys and to authenticate devices and communications between them on networks.
Enables remote “brownfield” installation of hardware-based security

Synopsys AP PUF is a physical unclonable function (PUF)-based RoT component that can be applied easily to almost any MCU/SoC/ASIC and is fab and process agnostic.
This IP has been developed following an ISO 26262 functional-safety-compliant flow and meets the ISO 26262 Automotive Safety Integrity Level (ASIL) B fault metric.

Synopsys AP PUF is a physical unclonable function (PUF)-based RoT component that can be applied easily to almost any MCU/SoC/ASIC and is fab and process agnostic.
This IP has been developed following an ISO 26262 functional-safety-compliant flow and meets the ISO 26262 Automotive Safety Integrity Level (ASIL) B fault metric.

The HDCP 2.3 ESMs are designed to support up to four ports. They protect HD and Ultra HD uncompressed audio-visual content and are fully compliant with the HDCP 2.3 standard for HDMI - and DisplayPort-based systems.
The self-contained cores include all the necessary components required to meet the HDCP 2.3 specification such as key-stream generation, content encryption and decryption, authentication and key exchange, and system renewability.

Complete, self-contained security modules with hardware Root of Trust
Transmitter (TX), Receiver (RX) and Repeater (Rep) solutions
Silicon-proven. Widely deployed. Certified.
Compliant with the latest HDCP 2.3 content protection standard (backwards compatible with HDCP 2.2)

The Multiport/Multiprotocol HDCP 2.2/2.3 Embedded Security Modules (ESMs) are autonomous modules that provide designers with complete and robust transmitter (TX), receiver (RX) and repeater (Rep) implementations of the HDCP 2.3 content protection technology over HDMI 2.1/2.0, DisplayPort 2.0/1.4, and USB 3.x Type-C wired connections.
These solutions help designers shorten development cycles and fully meet the stringent security requirements of the DCP LLC licensing authority.