Cadence provides a mature and comprehensive Verification IP (VIP) for the CCIX specification which is an open standard for a new class of server products that addresses the challenging performance and latency requirements in the growing data center market. Incorporating the latest protocol updates, the Cadence® Verification IP for CCIX provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Cadence provides a solution for interconnect verification that supports the verification of coherent interconnect. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for CCIX helps you reduce time to test, accelerate verification closure, and ensure end-product quality.
The CCIX VIP showcases Cadence’s pioneering efforts in the enterprise data center market by being the first to announce a VIP-DIP solution. With early customer engagements prior to specification ratification and joint collaboration with Cadence DIP, this VIP allows customers to leverage our expertise in PCIe and cache coherency from the verification and design spectrum.
Built on top of known and proven PCIe and AMBA verification solutions, the CCIX VIP runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).
Supported specification: The Protocol Layer of CCIX 1.0, 1.1, and 2.0 specifications.
