PCIe Over Optical: Transforming High-Speed Data Transmission
With the rise in AI requiring new computing models and enhanced data transmission methods to cope, the necessity for innovative, high-performance, and low-latency connectivity solutions has never been more apparent. PCIe over Optical is set to play a key role in enabling the growth of AI and here we examine some of the intricacies of PCIe over Optical to explore its implementation, challenges, and potential.
The Driving forces
The data center landscape is undergoing a transformative shift. AI models, such as ChatGPT, have escalated rapidly, from 1.5 billion parameters (ChatGPT 2.0) to 175 billion parameters for ChatGPT 4.0. The next-generation/s of generative AI (genAI) platforms are expected to use somewhere in the region of 100 trillion parameters, which (adding context) is approximately the same number of synapses in a human brain. And this necessitates immense data processing capabilities.
Relentless growth in data consumption leads to exponentially increasing demands on data center networks, with global data creation set to reach more than 180 zettabytes by next year. This is up 50% on 2023. And up 200% on 2020.
This surge in data volume underscores the need for robust connectivity solutions capable of handling high-speed data transfer with minimal latency.
Disaggregated computing is becoming a critical model in enabling this, with memory and storage being shared in centralized pools for enhanced efficiency and capacity. This model relies on low-latency connectivity solutions. As distances grow and rates increase, linear pluggable optics (LPOs) are a potential solution for distribution. When direct attached cables are not capable of meeting the reach demand, LPOs support longer reach with minimal latency and power impact.
And unlike traditional, fully retimed optical transceivers, LPOs eliminate the clock data recovery (CDR) and digital signal processing (DSP) components, resulting in lower power consumption and latency versus typical optical pluggables.
This simplification, however, requires highly sophisticated SerDes technology to ensure interoperability and efficient data transmission.
Related Semiconductor IP
- Specialty PCI IO IP, BOAC (Bonding Over Active Circuit), UMC 65nm SP process
- Specialty PCI IO IP, BOAC (Bonding Over Active Circuit), UMC 0.18um G2 process
- Specialty PCI IO IP, BOAC (Bonding Over Active Circuit), 5V tolerance, UMC 0.18um G2 process
- Specialty PCI IO IP, BOAC (Bonding Over Active Circuit), UMC 0.13um HS/FSG process
- Specialty PCI IO IP, BOAC (Bonding Over Active Circuit), 5V tolerance, UMC 0.13um HS/FSG process
Related Blogs
- CCIX Over PCIe: Faster Coherent Interconnects for AI, Networking, 4G/5G, and Storage Designs
- The Future of PCIe Is Optical: Synopsys and OpenLight Present First PCIe 7.0 Data-Rate-Over-Optics Demo
- Cadence Showcases World's First 128GT/s PCIe 7.0 IP Over Optics
- PCIe Verification IP Overview
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?