PCIe Verification IP Overview
In this video, VIP Senior Manager Paul Graykowski of Synopsys gives an overview of the PCI Express Verification IP.
Related Semiconductor IP
- Multi-channel, multi-rate Ethernet aggregator - 10G to 400G AX (e.g., AI)
- Multi-channel, multi-rate Ethernet aggregator - 10G to 800G DX
- 200G/400G/800G Ethernet PCS/FEC
- 50G/100G MAC/PCS/FEC
- 25G/10G/SGMII/ 1000BASE-X PCS and MAC
Related Blogs
- Industry's First Verification IP for PCIe 7.0
- PCIe Spread Spectrum Clocking (SSC) for Verification Engineers
- Check Again: Cadence Announces Release of the First PCIe 5.0 VIP - With TripleCheck!
- Integration and Verification of PCIe Gen4 Root Complex IP into an Arm-Based Server SoC Application