The CCIX Controller IP implements the port logic required to build a root port, endpoint, switch or dual mode device. The configurable and scalable IP is compliant with the latest CCIX specification, and supports all required features of the PCI Express 4.0, 3.1, 2.1, and 1.1 and PHY Interface for PCI Express (PIPE) specifications. The IP supports cache coherency as defined by the CCIX standard allowing processors and accelerators to use shared memory faster. The high-quality, synthesizable IP is available in your choice of datapath widths, PIPE interface widths, operating frequencies, and over 1200 configuration parameters all working together to enable designers to optimize their applications for size, power, latency and throughput. The CCIX Controller IP integrates quickly and easily into system-on-chip (SoC) designs with the native application interface or an industry standard AMBA interface, and provides attainable timing closure in modern silicon processes.
The CCIX Controller IP is built upon the successful Synopsys IP for PCI Express which has been silicon validated in over 1800 designs with multiple hardware platforms, PHYs and PCIe verification suites, thereby reducing risk and improving time-to-market.
