Building a robust HBM2 PHY
February 20, 2017
What is HBM?
HBM is a high-performance memory that features reduced power consumption and a small form factor. More specifically, it combines 2.5D packaging with a wider interface at a lower clock speed (as compared to DDR4) to deliver higher overall throughput at a higher bandwidth-per-watt efficiency for high-performance computing applications.
To read the full article, click here
Related Semiconductor IP
- HBM3 PHY
- TSMC CLN3FFP HBM4 PHY
- HBM3 PHY V2 (Hard) - TSMC N3P
- TSMC CLN16FFGL+ HBM PHY IP
- HBM3 PHY & Controller
Related Blogs
- Rambus highlights HBM2 PHY collaboration at GLOBALFOUNDRIES Technology Conference
- Need to develop robust Indian semicon industry, led by local companies!
- How many people does it take to design an SoC? - Redux. Building brains with processors.
- Cadence support for the Open NAND Flash Interface (ONFI) 3.0 controller and PHY IP solution + PCIe Controller IP opening the door for NVM Express support