IGAHBMZ03A is a High Bandwidth Memory 4 Physical Layer (HBM4 PHY) that is compliant with JEDEC HBM4 DRAM Specification JESD270-4. Fabricated in the TSMC 3 nm Advanced process node (N3P), it supports the data rate up to 12 Gbps per data pin in the DDR PHY Interface (DFI)-like 1:4 clock frequency ratio (HBM4 controller clock: WDQS = 1:4). The signal and power integrity is analyzed by the GUC design flow to meet all signal and power requirements.
GUC HBM4 PHY includes a hard PHY and a Register Transfer Level (RTL) soft module. The hard PHY, IGAHBMZ03A, includes Command Address (CA) modules, data modules, IO pads, a Phase-Locked Loop (PLL), and Delay-Locked Loops (DLLs). The RTL soft module, also called Miscellaneous Logic Block (MLB), included to work with the hard PHY for functions, such as the training logic, the register controller interface, the Built-In Self-Test (BIST) logic, and the IEEE 1500 function logic.
