Cadence support for the Open NAND Flash Interface (ONFI) 3.0 controller and PHY IP solution + PCIe Controller IP opening the door for NVM Express support
April 12, 2012
The press release about ONFI 3.0 support was launched by Cadence at the beginning of this year. It was a good illustration of Denali, then Cadence, long term commitment to Nand Flash Controller IP support. The ONFI 3 specification simplifies the design of high-performance computing platforms, such as solid state drives and enterprise storage solutions; and consumer devices, such as tablets and smartphones that integrate NAND Flash memory. The new specification defines speeds of up to 400 mega-transfers per second. In addition to the new ONFI 3 specification, the Cadence Flash and controller IP also support the Toggle 2.0 specification.
To read the full article, click here
Related Semiconductor IP
- Network-on-Chip (NoC)
- 12-bit, 400 MSPS SAR ADC - TSMC 12nm FFC
- UCIe PHY (Die-to-Die) IP
- UCIe-S 64GT/s PHY IP
- UA Link DL IP core
Related Blogs
- Unlocking the Power of NAND ONFI Controller IP
- Rambus HBM3 Controller IP Gives AI Training a New Boost
- New CXL 3.1 Controller IP for Next-Generation Data Centers
- Rambus LPDDR5T/5X/5 Controller IP Turbocharges AI Inference Performance to 9.6 Gbps
Latest Blogs
- Design specification: The cornerstone of an ASIC collaboration
- The importance of ADCs in low-power electrocardiography ASICs
- VESA Adaptive-Sync V2 Operation in DisplayPort VIP
- Design, Verification, and Software Development Decisions Require a Single Source of Truth
- CAVP-Validated Post-Quantum Cryptography