SkyeChip’s High Bandwidth Memory (HBM) IP consists of a PHY and memory controller optimized for TSMC N7, N12 and Samsung 4nm process to support the HBM3 memory standard operating at up to 6.4 Gbps/pin. SkyeChip’s HBM IP is designed for high memory throughput and low latency applications while minimizing area and power consumption.
SkyeChip’s HBM IP is available either as a standalone HBM3 PHY that communicates with a memory controller over a modified variant of the DDR PHY Interface (DFI) 5.0 standard or as a combination of both the HBM3 PHY and the HBM3 memory controller as shown in Figure 1. The HBM3 PHY is provided as a hard HBM3 PHY IP that is primarily delivered as GDSII inclusive of its own PLL and the HBM3 I/Os. The HBM3 PHY is also equipped with a hardware-assisted embedded microcontroller that is responsible to train and optimize the channel timings of the memory interface. The hardware-assisted embedded microcontroller provides the flexibility to perform firmware-based training algorithms and interface tests.
HBM3 PHY & Controller
Overview
Key Features
- Mainband to initiate reads and writes to the memory – multi-port per pseudo channel capability available via NoC add-on block
- Sideband for exception, error handling and firmware delivery
- Interface to the HBM3 PHY
- Flexibility to customize the mapping of the host memory map
- Support for 4H, 8H, 12H and 16H die stacks
- Support for out-of-order scheduling for best memory bus efficiency with configurable paging policies and priority scheduling
- Anti-starvation scheme to ensure QoS is met
- Support for partial writes included
- Native support for basic RAS features like command parity, ECS, RFM, ECC (SEC-DED), data scrambling and temperature-compensated refresh – enhanced RAS engine available as an add-on core
- Support for system-controlled or auto self-refresh, power-down and refresh handling, pulled-in or postponed refreshes and throttling and trips due to thermal events
- Support memory BIST for DRAM and internal SRAM and scan
- Support for NoC add-on block and RAS and debug (observation, logical loopback, traffic generator/checker) engines
Benefits
- One stop PHY & Controller solution with an average random efficiency of more than 85%
- Supports up to 6400 MT/s
- DFI 5.0 compatible interface to the memory controller
- Flexible PHY with programmable intelligent interface training sequences
- Flexible IEEE1500 interface to support memory vendor customizations
- Supports up to 32Gb density per die
- Supports major 2.5D/3D packaging technologies including support for interposer designs and interconnect and memory repairs
- Add-on features/engines for MPFE, RAS and Debug available upon request
- Add-on feature for generic 2.5D die-to-die data transport interconnect
Applications
- Data center and networking
- High performance computing (HPC)
- Artificial intelligence (AI)
- High-end graphics
Deliverables
- Executable .run installation file
- GDSII, LEF Files, LVS netlists, .lib/.db
- timing models, Verilog model, DRC/LVS log files, I/O IBIS model, I/O HSPICE netlist, parameterized Verilog top-level PHY netlist files
- sample verification environment, PHY data book
- physical implementation guide, application notes, verification guide, installation guide, implementation checklist
- The PHY Utility Block includes Verilog code, synthesis/STA constraints and scripts, sample verification environment, data book
Technical Specifications
Foundry, Node
TSMC N12, N7, SF4
Availability
Now at SkyeChip.com