Breaking Down the "Make vs. Buy" Barriers for IP
February 27, 2012
As the fabless era disaggregated EDA and IP offerings, there are areas where in- house development is still the norm, even with today’s $2.5B IP industry. One of these is on-chip network – connecting the IP cores and memory subsystem.
On-chip interconnect or networks-on-chip (NoCs), in many companies, is still regarded as a part of the IP that can be internally developed for SoCs. With deeper process nodes, such as 28nm, enabling device convergence, more cores are included in the SoC, accelerated further by subsystems.
Related Semiconductor IP
- Smart Network-on-Chip (NoC) IP
- NoC System IP
- Cloud-active NOC configuration tool for generating and simulating Coherent and Non-Coherent NoCs
- Tessent NoC Monitor
- Network-on-Chip (NoC) Interconnect IP
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- AI-Based Sequence Detection for IP and SoC Verification & Validation
- Ensuring IP Quality for a Better IP Experience