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Compare 54 IP from 22 vendors (1 - 10)
  • Network-on-Chip (NoC)
    • InfiniNoC is a highly customizable Network-on-Chip (NoC) from InfiniNode Technologies, designed to provide a scalable, high-performance communication backbone for next-generation SoCs.
    • It enables seamless integration of diverse IP blocks while delivering the flexibility, scalability, and performance required to accelerate complex chip development.
    • The architecture supports high bandwidth and low latency alongside energy-efficient data movement, and it can be customized to match specific use cases and requirements.
    Block Diagram -- Network-on-Chip (NoC)
  • NoC Verification IP
    • Complex network with acyclic agent graph (DAG). Layered and parallel NOC is also supported.
    • Any number of master and slave ports is supported. Each port can be configured individually.
    • ARM® AHB3-Lite,5, ARM® AXI 3,4,4-Lite,5,5-Lite, ARM® APB 2,3,4,5, SiFive TileLink Tl-UL, Tl-UH, TL-C.
    Block Diagram -- NoC Verification IP
  • Smart Network-on-Chip (NoC) IP
    • Smart NoC automation
    • Topology generation with minimum wire length
    • Scripting-driven regular topology creation
    • Incremental design capability
    • Auto-timing closure assist
    Block Diagram -- Smart Network-on-Chip (NoC) IP
  • NoC System IP
    • Packetization allows a reduction of the wire count
    • Significant reduction of the complexity of large crossbars by partitioning them into smaller ones
    • Introduction of pipelining to links with heavy loads, allowing the NoC to operate faster
    Block Diagram -- NoC System IP
  • Cloud-active NOC configuration tool for generating and simulating Coherent and Non-Coherent NoCs
    • Drag & Drop Graphical User Interface
    • Unified configuration tree view
    • Intelligent routing path calculation
    Block Diagram -- Cloud-active NOC configuration tool for generating and simulating Coherent and Non-Coherent NoCs
  • Tessent NoC Monitor
    • Full transaction and trace-level visibility of traffic
    • Wide range of measurements, analytics statistics: transactions, bus cycles, latency, duration, beats, concurrency
    Block Diagram -- Tessent NoC Monitor
  • Network-on-Chip (NoC) Interconnect IP
    • AMBA AXI / APB / AHB protocol compliant
    • Configurable number of masters and slaves
  • Coherent Network-on-chip (NoC) IP
    • Layered, scalable, configurable, and physically aware configurable NoC
    Block Diagram -- Coherent Network-on-chip (NoC) IP
  • Non-coherent Network-on-chip (NoC) IP
    • Layered, scalable, physically aware configurable NoC
    Block Diagram -- Non-coherent Network-on-chip (NoC) IP
  • Coherent Network-on-Chip (NOC)
    • Node Protocols: ACE4, ACE5 and CHI
    • Architected to significantly reduce routing congestion for many-core systems
    • Integrated with SkyeChip’s Home Agent and swappable with any other proprietary coherency handlers
    • Supports operating frequencies up to 2GHz with assists in high frequency timing closures
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Semiconductor IP