Noc IP

Compare 50 IP from 19 vendors (1 - 10)

Tessent NoC Monitor
- Full transaction and trace-level visibility of traffic
- Wide range of measurements, analytics statistics: transactions, bus cycles, latency, duration, beats, concurrency
Coherent Network-on-chip (NoC) IP
- Layered, scalable, configurable, and physically aware configurable NoC
Non-coherent Network-on-chip (NoC) IP
- Layered, scalable, physically aware configurable NoC
NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
- Easy to integrate the NoC Silicon IP using interface
- N master and M slave ports based on customer requirement
- Supports wide range of memory map.
High speed NoC (Network On-Chip) Interconnect IP
- High Performance
- Low Power Consumption
- Smaller Area
NoC System IP
- Packetization allows a reduction of the wire count
- Significant reduction of the complexity of large crossbars by partitioning them into smaller ones
- Introduction of pipelining to links with heavy loads, allowing the NoC to operate faster
Cloud-active NOC configuration tool for generating and simulating Coherent and Non-Coherent NoCs
- Drag & Drop Graphical User Interface
- Unified configuration tree view
- Intelligent routing path calculation
Coherent Network-on-Chip (NoC)
- External interface protocols: ACE4, ACE5 and CHI
- Architected to significantly reduce routing congestion for many-core systems
- Integrated with SkyeChip’s Home Agent and swappable with any other proprietary coherency handlers
- Supports operating frequencies up to 2GHz with assists in high frequency timing closures
Non-Coherent Network-on-Chip (NoC)
- External Interface Protocols: AXI4, AXI5, AXI-Stream, APB and proprietary protocols
- Architected to reduce routing congestion and to ease high frequency timing closure
- Supports operating frequencies up to 2GHz
- Supports source synchronous and synchronous clocking topologies
Network-on-Chip (NoC) Interconnect IP
- AMBA AXI / APB / AHB protocol compliant
- Configurable number of masters and slaves

NoC IP