Audio Interface IP

Audio Interface IP Cores support a wide range of industry-standard protocols such as I²S (Inter-IC Sound), TDM (Time-Division Multiplexing), SPDIF, and PDM (Pulse-Density Modulation), enabling reliable transmission and reception of digital audio signals in embedded systems.

Explore our vast directory of Audio Interface IP Cores below.

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Compare 35 Audio Interface IP from 16 vendors (1 - 10)
  • I2S Controller
    • I²S Controller is designed to transfer audio data to and from Audio codec.
    • It can be configured as both Master and Slave mode using software.
    • The I²S IP is Phillips Inter IC Sound (I²S) specification compliant core for Altera devices.
    Block Diagram -- I2S Controller
  • I2S Verification IP
    • Complies with Philips I2S Specification June 5, 1996
    • Full I2S Transmitter, Receiver and Controller functionality
    • Supports up to 32 channels in transmit path
    • Supports up to 32 channels in receive path
    Block Diagram -- I2S Verification IP
  • I2S Controller IIP
    • Compliant with the Philips I2S Bus Specification
    • Master mode as Controller
    • Slave mode as transmitter and receiver
    • Bidirectional operation through two unidirectional serial data lines
    Block Diagram -- I2S Controller IIP
  • I2S Synthesizable Transactor
    • Supports Philips I2S Bus Specification June 5, 1996
    • Full I2S Transmitter, Receiver and Controller functionality
    • Supports up to 32 channels in transmit path
    • Supports up to 32 channels in receive path
    Block Diagram -- I2S Synthesizable Transactor
  • Simulation VIP for I2S
    • Configurability
    • Fully configurable VIP configuration: Manager/Subordinate, Transmitter/Receiver, Active/Passive
    • Word Length Programmability
    • Supports 8, 12, 16, 20, 24, 32, and user-defined
    Block Diagram -- Simulation VIP for I2S
  • I2S - Ensures proper audio data transmission, synchronization, and integrity
    • I2S (Inter-IC Sound) is a serial bus interface used for connecting digital audio devices. As a Verification IP (VIP), it ensures proper data transmission, signal integrity, timing, and protocol compliance in audio communication systems.
    • This VIP verifies key elements such as word length, frame synchronization, clock behavior, and error handling, making it essential for testing I2S communication in a range of applications, including consumer electronics, automotive, and medical devices
    Block Diagram -- I2S - Ensures proper audio data transmission, synchronization, and integrity
  • I2S/TDM Serial Audio Interface with Asynchronous Sample Rate Conversion
    • The IPB-I2S-TDM-ASRC combines an I2S/TDM configurable serial audio interface with two embedded stereo Asynchronous Sample Rate Converters (ASRCs).
    • The ASRCs can provide very high quality in terms of harmonic distortion and noise, tolerance and rejection of input jitter.
    Block Diagram -- I2S/TDM Serial Audio Interface with Asynchronous Sample Rate Conversion
  • AC97 Audio Controller
    • Fixed 48kHz audio support
    • Hardware variable sample rate support from 8kHz to 48kHz (up to 96kHz with Double Rate Audio enabled)
    • Double Rate Audio support for Left, Right and Center channels
    • 16 bit sample size support (18 and 20 bit support planned in future)
    Block Diagram -- AC97 Audio Controller
  • AC97 Controller IIP
    • Compliant with AC'97 2.2 specification
    • Supports AC'97 audio codec functionality
    • Supports variable and fixed sample rate support
    • Supports 16, 18 and 20 bit sample size support
    Block Diagram -- AC97 Controller IIP
  • AC'97 Audio Controller
    • The AC97-CTRL Audio Controller is a configurable IP block designed to simplify the integration of the AC'97 audio interface into ASIC and FPGA designs.
    • Fully compliant with the Intel Audio Codec '97 (AC’97) Revision 2.3 specification, this controller facilitates reliable transmission and reception of stereo or multi-channel audio streams using the well-established AC-Link interface.
    • With support for a single codec operating at a standard 48 kHz sample rate, the core is ideal for embedded applications that demand proven audio infrastructure with a compact silicon footprint and efficient data handling.
    Block Diagram -- AC'97 Audio Controller
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