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Search (449)
Compare 449 RAM IP from 28 vendors (1 - 10)
  • CodaCache® Last Level Cache IP
    • Standalone IP
    • 1.2 GHz frequency in 16FF+TT process
    • Protocol interoperability: AMBA AXI 4
    Block Diagram -- CodaCache® Last Level Cache IP
  • Single Rail SRAM GLOBALFOUNDRIES 22FDX
    • Single port SRAM compiler based on Racyics® R188 logic memory cell with dual-well architecture
    • Supply voltage 0.55 V to 0.8 V enabled with Racyics® ABB
    Block Diagram -- Single Rail SRAM GLOBALFOUNDRIES 22FDX
  • Dual-Rail SRAM Globalfoundries 22FDX
    • Single port SRAM compiler based on P124 bitcell with Dual-supply-rail architecture
    • Bitcell array supply voltage 0.8V and ULV core interface down to 0.4V enabled with Racyics' ABB
    Block Diagram -- Dual-Rail SRAM Globalfoundries 22FDX
  • Ultra Low Power Embedded SRAM - Samsung 28FDSOI
    • Single port, single voltage rail synchronous SRAM
    • Hierarchical Bit Line – subdividing the array into columns/ rows, banks and local blocks.
    • Configurable mux factor sets column length and overall aspect ratio
    • Bit Line Voltage control eliminates potential low operating voltages issues
    Block Diagram -- Ultra Low Power Embedded SRAM - Samsung 28FDSOI
  • Ultra Low Power Embedded SRAM - TSMC 22ULL
    • Single port, single voltage rail synchronous SRAM
    • Hierarchical Bit Line – subdividing the array into columns/ rows, banks and local blocks.
    • Configurable mux factor sets column length and overall aspect ratio
    • Bit Line Voltage control eliminates potential low operating voltages issues
    Block Diagram -- Ultra Low Power Embedded SRAM - TSMC 22ULL
  • Ultra Low Voltage Embedded SRAM - TSMC 22ULL
    • Single port, single voltage rail synchronous SRAM
    • Hierarchical Bit Line Architecture – sub-diving the array into columns/rows, banks and local blocks
    • ‘Smart Assist’ – controls voltage drive to selected bit cells and bit lines in read and write cycles
    • Pre-charge mux sense – read circuit that helps reduce both active and leakage power in the memory array
    Block Diagram -- Ultra Low Voltage Embedded SRAM - TSMC 22ULL
  • Ultra Low Power Embedded SRAM - TSMC 28HPC+
    • Single port, single voltage rail synchronous SRAM
    • Hierarchical Bit Line – subdividing the array into columns/ rows, banks and local blocks.
    • Configurable mux factor sets column length and overall aspect ratio
    • Bit Line Voltage control eliminates potential low operating voltages issues
    Block Diagram -- Ultra Low Power Embedded SRAM - TSMC 28HPC+
  • Ultra Low Voltage Embedded SRAM - TSMC 28HPC+
    • Single port, single voltage rail synchronous SRAM
    • Hierarchical Bit Line Architecture – sub-diving the array into columns/rows, banks and local blocks
    • ‘Smart Assist’ – controls voltage drive to selected bit cells and bit lines in read and write cycles
    • Pre-charge mux sense – read circuit that helps reduce both active and leakage power in the memory array
    Block Diagram -- Ultra Low Voltage Embedded SRAM - TSMC 28HPC+
  • Ultra Low Voltage Embedded SRAM - TSMC 40ULP
    • Single port, single voltage rail synchronous SRAM
    • Hierarchical Bit Line Architecture – sub-diving the array into columns/rows, banks and local blocks
    • ‘Smart Assist’ – controls voltage drive to selected bit cells and bit lines in read and write cycles
    • Pre-charge mux sense – read circuit that helps reduce both active and leakage power in the memory array
    Block Diagram -- Ultra Low Voltage Embedded SRAM - TSMC 40ULP
  • Single Port SRAM Compiler GF22FDX Low Power
    • Silicon proven Single Port SRAM compiler for GF22 FDX - Memory optimized for low power and supports body biasing.
    Block Diagram -- Single Port SRAM Compiler GF22FDX Low Power
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