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Single Rail SRAM GLOBALFOUNDRIES 22FDX
- Ultra-low voltage logic designs using adaptive body biasing demand dense SRAM solutions which fully integrate in the ABB aware implementation and sign-off flow of the Racyics® ABX Platform solution.
- The Racyics® Single Rail SRAM supports ultra-low voltage operation down to 0.55 V where logic designs with Minimum-Energy-Point are implemented.
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Dual Rail SRAM Globalfoundries 22FDX
- Single port SRAM compiler based on P124 bitcell with Dual-supply-rail architecture
- Bitcell array supply voltage 0.8V and ULV core interface down to 0.4V enabled with Racyics' ABB
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Low Power Memory Compiler - Single Port SRAM - GF 22nm FDX
- Silicon proven Single Port SRAM compiler for GF22 FDX - Memory optimized for low power and supports body biasing.
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MRAM Synthesizable Transactor
- Supports all the MRAM commands as per the MR2A16A and MR0A08B specifications.
- Supports Symmetrical high-speed read and write with fast access time.
- Supports SRAM Compatible timing
- Supports native non-volatility
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Ultra Low Power Embedded SRAM - Samsung 28FDSOI
- Single port, single voltage rail synchronous SRAM
- Hierarchical Bit Line – subdividing the array into columns/ rows, banks and local blocks.
- Configurable mux factor sets column length and overall aspect ratio
- Bit Line Voltage control eliminates potential low operating voltages issues
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Ultra Low Power Embedded SRAM - TSMC 22ULL
- Single port, single voltage rail synchronous SRAM
- Hierarchical Bit Line – subdividing the array into columns/ rows, banks and local blocks.
- Configurable mux factor sets column length and overall aspect ratio
- Bit Line Voltage control eliminates potential low operating voltages issues
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Ultra Low Voltage Embedded SRAM - TSMC 22ULL
- Single port, single voltage rail synchronous SRAM
- Hierarchical Bit Line Architecture – sub-diving the array into columns/rows, banks and local blocks
- ‘Smart Assist’ – controls voltage drive to selected bit cells and bit lines in read and write cycles
- Pre-charge mux sense – read circuit that helps reduce both active and leakage power in the memory array
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Ultra Low Power Embedded SRAM - TSMC 28HPC+
- Single port, single voltage rail synchronous SRAM
- Hierarchical Bit Line – subdividing the array into columns/ rows, banks and local blocks.
- Configurable mux factor sets column length and overall aspect ratio
- Bit Line Voltage control eliminates potential low operating voltages issues
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Ultra Low Voltage Embedded SRAM - TSMC 28HPC+
- Single port, single voltage rail synchronous SRAM
- Hierarchical Bit Line Architecture – sub-diving the array into columns/rows, banks and local blocks
- ‘Smart Assist’ – controls voltage drive to selected bit cells and bit lines in read and write cycles
- Pre-charge mux sense – read circuit that helps reduce both active and leakage power in the memory array
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Ultra Low Voltage Embedded SRAM - TSMC 40ULP
- Single port, single voltage rail synchronous SRAM
- Hierarchical Bit Line Architecture – sub-diving the array into columns/rows, banks and local blocks
- ‘Smart Assist’ – controls voltage drive to selected bit cells and bit lines in read and write cycles
- Pre-charge mux sense – read circuit that helps reduce both active and leakage power in the memory array
