Register File IP

Compare 249 Register File IP from 13 vendors (1 - 10)

Ultra High-Speed Cache Memory Compiler
- Up to 3.4 GHz operation in N3P process
- Cache size up to 16 Kb
- 4 – 64-bit word width
- Configurable way associativity
1-Port Register File Compiler GF22FDX Low Power

Silicon proven 1-Port Register File SRAM compiler for GF22 FDX - Memory optimized for low power and supports body biasing.
Register File with low power retention mode and 3 speed options
- Ultra low power data retention. Memory instances generated by the RF1P-ULL-GF22FDX go into a deep sleep mode that retains data at minimal power consumption.
- Self biasing. The RF1P-ULL-GF28FDX internal self-biasing capabilities provide ease of IP integration.
- High yield. To ensure high manufacturing yield, the RF1P-ULL-GF22FDX utilizes GLOBALFOUNDRIES’ low leakage 6T (0.110µ2) bit cells and is consistent with Design for Manufacturing (DFM) guidelines for the 22nm FDX process.
- High usability. All signal and power pins are available on metal 4 while maintaining routing porosity in metal 4. Power pins can optionally be made available on metal 5 to simplify the power connections at the chip level.
Tuneable multi-port register file architecture
- Custom Register File Architecture
- Power savings >50%
- Wide operating voltage range
TSMC CLN6FF Asynchronous Read Two Port Register File Compiler
- Pins and metal layers
- General
Single Port Register File compiler - Memory optimized for high density and high speed - compiler range up to 40 k
- Configuration
- SVT transistors for memory periphery
- uHD HVT pushed rule bit-cell from foundry
- High speed
Two Port Register File compiler - Memory optimized for high density and low power - Dual Voltage - compiler range up to 64 k
- 1. Reduce the die cost
- Unique architecture optimizing the periphery area for outstanding area gain
- 2. Extend the battery life
- Leakage reduction thanks to careful design structures,optional retention mode and choice of SVT/HVT periphery
Single Port Register File compiler - Memory optimized for high density and speed - Dual Voltage - Compiler range up to 40 kbits
- Decrease of fabrication costs
- Up to 50% denser than traditional register file compilers!
- Ultra low dynamic power
- Low power architecture even at nominal voltage: Up to 50% less consuming than standard memory compilers available at 90 nm LP
Two Port Register File compiler - Memory optimized for high density and low power optimized - compiler range up to 40 k
- Reduce the die cost
- Unique architecture optimizing the periphery area for outstanding area gain
- Routing allowed upwards from Metal 4, Support Metal 5 top Metal option
- Extend the battery life
Two Port Register File compiler - Memory optimized fore high density and high speed - compiler range up to 320 k
- Reduced the die cost
- Unique architecture optimizing the periphery area for outstanding area gain
- Routing allowed upwards from Metal 4, Support Metal 5 top Metal option
- Extend the battery life