The sFIFO controls are designed to operate over a wide range of clock frequencies. The interface signals are fully synchronous; no asynchronous signals are present on either side. Only reset may be asynchronous in that it may be asserted asynchronously and synchronized internally to the clock.
The FIFO also has a programmable fall-through for first data entering an empty FIFO. It may be “0” in which case the input is passed combinatorially to the output, or “1” where the FIFO appears like a simple register.
