IP Catalog > DSP & Math IP > Building Blocks IP > Accelerator IP

Accelerator IP

Welcome to the ultimate Accelerator IP hub! Explore our vast directory of Accelerator IP
All offers in Accelerator IP
Filter
Filter

Login required.

Sign in

Login required.

Sign in

Login required.

Sign in

Search (23)
Compare 23 Accelerator IP from 14 vendors (1 - 10)
  • Radar processing IP suite for Advanced Driver Assistance Systems
    • The eSi-ADAS™ is a suite of radar accelerator IP including a complete Radar co-processor engine, they enhance the overall performance and capabilities of radar  systems for automotive, drone and UAV applications that require fast and responsive situational awareness.
    • The IP has been licensed to some of the leading automotive Tier 1 and Tier 2 suppliers and is in production vehicles.
    Block Diagram -- Radar processing IP suite for Advanced Driver Assistance Systems
  • IP cores for ultra-low power AI-enabled devices
    • Ultra-fast Response Time
    • Zero-latency Switching
    • Low Power
    Block Diagram -- IP cores for ultra-low power AI-enabled devices
  • Fusion Recurrent Neural Network (RNN) Accelerator
    • MAC utilization up to 99%
    • Energy efficiency 2.06 TOPS/W
    • Peak performance can scale up to 204.8 GOPS
    Block Diagram -- Fusion Recurrent Neural Network (RNN) Accelerator
  • Constant False Alarm Rate Processor (CFAR)
    • Removes a compute intensive task away from the microprocessor to a predictable, low-latency offload engine
    Block Diagram -- Constant False Alarm Rate Processor (CFAR)
  • Convolutional Neural Network (CNN) Compact Accelerator
    • Support convolution layer, max pooling layer, batch normalization layer and full connect layer
    • Configurable bit width of weight (16 bit, 1 bit)
    Block Diagram -- Convolutional Neural Network (CNN) Compact Accelerator
  • ADPCM G.726 Codec
    • Compliant with ITU G.721, G.723, G.726 and G.726-Annex recommendations.
    • On-the-fly configuration for variable compression rate, PCM law.
    • Process capability of up to 64 full duplex or up to 128 half duplex voice channels.
    • Burst and continuous mode support.
    Block Diagram -- ADPCM G.726 Codec
  • Floating-point (IEEE 754) IP based on Arria 10 and Stratix 10 FPGAs
    • FFT size: Any size power-of-two or non-power-of-two
    • Dynamic Range: IEEE754 single precision floating point
    Block Diagram -- Floating-point (IEEE 754) IP based on Arria 10 and Stratix 10 FPGAs
  • WebM VP8 Video Decoder Hardware IP
    • Silicon area: 383kGates, 40kBytes of single port SRAM
    • Synthesizable clock frequency: up to 290 MHz (TSMC65nm LP, topographical synthesis)
    • Easy back-end: Single clock domain;low number of isolated single port SRAM and clock gating elements; no dual port memories.
    • Performance configuration: choose internal memory size according to your resolution requirement - up to 2160p.
    Block Diagram -- WebM VP8 Video Decoder Hardware IP
  • 256 8-bit-MAC DSP core
    • High performance vector signal processing and efficient control code processing
    • 256 8-bit macs, or 128 16-bit macs, or 32-bit macs per cycle
    • Flexible vector permute operations
    • Maskable vector lanes
  • 32 8-bit-MAC Vector DSP Core
    • High performance vector signal processing and efficient control code processing
    • 32 8-bit macs, or 16 16-bit macs, or 8 32-bit macs per cycle
    • Flexible vector permute operations
    • Maskable vector lanes
×
Semiconductor IP