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Accelerator IP

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Search (26)
Compare 26 Accelerator IP from 17 vendors (1 - 10)
  • Radar processing IP suite for Advanced Driver Assistance Systems
    • The eSi-ADAS™ is a suite of radar accelerator IP including a complete Radar co-processor engine, they enhance the overall performance and capabilities of radar  systems for automotive, drone and UAV applications that require fast and responsive situational awareness.
    • The IP has been licensed to some of the leading automotive Tier 1 and Tier 2 suppliers and is in production vehicles.
    Block Diagram -- Radar processing IP suite for Advanced Driver Assistance Systems
  • IP cores for ultra-low power AI-enabled devices
    • Ultra-fast Response Time
    • Zero-latency Switching
    • Low Power
    Block Diagram -- IP cores for ultra-low power AI-enabled devices
  • Edge AI Accelerator NNE 1.0
    • Minimum efforts in system integration
    • Speed up AI inference performance
    • Super performance for power sensitive application
    Block Diagram -- Edge AI Accelerator NNE 1.0
  • Convolutional Neural Network (CNN) Compact Accelerator
    • Support convolution layer, max pooling layer, batch normalization layer and full connect layer
    • Configurable bit width of weight (16 bit, 1 bit)
    Block Diagram -- Convolutional Neural Network (CNN) Compact Accelerator
  • Floating-point (IEEE 754) IP based on Arria 10 and Stratix 10 FPGAs
    • FFT size: Any size power-of-two or non-power-of-two
    • Dynamic Range: IEEE754 single precision floating point
    Block Diagram -- Floating-point (IEEE 754) IP based on Arria 10 and Stratix 10 FPGAs
  • Versatile DSP accelerator IP core
    • Versatile DSP accelerator IP core,
    • Excellent combination of small silicon footprint, computational power and low energy consumption,
    • Advanced loop control mechanisms to reduce code size and increase energy efficiency by switching off idle components during loop execution,
    • Use of tightly coupled data memory further contributes to low energy consumption and high processing efficiency,
    Block Diagram -- Versatile DSP accelerator IP core
  • WebM VP8 Video Decoder Hardware IP
    • Silicon area: 383kGates, 40kBytes of single port SRAM
    • Synthesizable clock frequency: up to 290 MHz (TSMC65nm LP, topographical synthesis)
    • Easy back-end: Single clock domain;low number of isolated single port SRAM and clock gating elements; no dual port memories.
    • Performance configuration: choose internal memory size according to your resolution requirement - up to 2160p.
    Block Diagram -- WebM VP8 Video Decoder Hardware IP
  • ADPCM G.726 Codec
    • Compliant with ITU G.721, G.723, G.726 and G.726-Annex recommendations.
    • On-the-fly configuration for variable compression rate, PCM law.
    • Process capability of up to 64 full duplex or up to 128 half duplex voice channels.
    • Burst and continuous mode support.
    Block Diagram -- ADPCM G.726 Codec
  • Fusion Recurrent Neural Network (RNN) Accelerator
    • MAC utilization up to 99%
    • Energy efficiency 2.06 TOPS/W
    • Peak performance can scale up to 204.8 GOPS
    Block Diagram -- Fusion Recurrent Neural Network (RNN) Accelerator
  • WCDMA Release 9 compliant Viterbi Decoder
    • 3GPP TS 25.212 V 9.5.0 Release 9
    • Supports all block sizes i.e., K=40 - 504.
    • Constraint length of 9
    Block Diagram -- WCDMA Release 9 compliant Viterbi Decoder
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