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Compare 274 Transform IP from 20 vendors (1 - 10)
  • 32-512 Point Streaming FFT Core
    • Supports 32/64/128/256/512-point complex FFT and IFFT and can switch dynamically
    • Inputs and outputs data in the natural order
    • Throughput of 1 sample (In-phase I + quadrature Q) per 4 clocks; no-gap processing of the input data
    • Parameterized bit width.
    Block Diagram -- 32-512 Point Streaming FFT Core
  • 128-Point FFT/IFFT IP Core
    • The FFT4T core implements a 128 point complex FFT and IFFT over 12 data streams in hardware. It runs at the clock frequency four times higher than the insput sampling frequency.
    • FFT4T core is a specialized FFT/IFFT processor intended for a situation where an RF signal is recieved over multiple channels in parallel and its filtering is to be performed in the frequency domain. The core fits nicely into, for example, a multichannel GPS system.
    Block Diagram -- 128-Point FFT/IFFT IP Core
  • ASIP-2 Programmable Filter Engine
    • Platform to design Application Specific Instruction Set Processors (ASIPs).
    • Ideal for supporting multi-standard systems.
    • Supports a wide range of complex DSP functions
    • The ASIP2 performs Fast Fourier Transform (FFT) to convert time domain signals to frequency domain signals for further processing. It supports FFT sizes from 4 to 8K.
    Block Diagram -- ASIP-2 Programmable Filter Engine
  • General-purpose FFT core
    • The FFT is factored into Radix-4 Butterfly operations. When an odd power of two is required, a small radix-2 “follower” stage performs the final iteration. The radix-2 stage does not require a full complex rotator so its cost is minimal.
    • The Radix-4 Engine fetches one complex word of data each clock cycle. Four interleaved data words are collected then applied to the t0-t3 inputs. On successive clock cycles the engine calculates the four frequency domain outputs f0-f3. These are then stored back into the Working Buffer.
    Block Diagram -- General-purpose FFT core
  • Discrete Cosine Transform
    • This core can perform the two dimensional Discrete Cosine Transform (DCT) and its inverse (IDCT) on an 8x8 block of samples.
    • The simple, fully synchronous design allows for fast operation while maintaining a low gate count.
    • It offers high performance and many features to meet your multimedia, digital video and digital printing applications
    Block Diagram -- Discrete Cosine Transform
  • Radar processing IP suite for Advanced Driver Assistance Systems
    • The eSi-ADAS™ is a suite of radar accelerator IP including a complete Radar co-processor engine, they enhance the overall performance and capabilities of radar  systems for automotive, drone and UAV applications that require fast and responsive situational awareness.
    • The IP has been licensed to some of the leading automotive Tier 1 and Tier 2 suppliers and is in production vehicles.
    Block Diagram -- Radar processing IP suite  for Advanced Driver Assistance Systems
  • Power-On Reset - Flexible Threshold (1­-1.3V), Ultra Low Current (100nA) - SilTerra 0.16µm CL160G
    • This macro-cell is an ultra low consumption Power-On Reset (POR) core designed for SilTerra 0.16μm CL160G CMOS technology.
    • The threshold sensing voltage can be configured from 1V to 1.3V (default is 1.15V). A hysteresis of 120mV is added to avoid false reset glitches in noisy supplies.
    Block Diagram -- Power-On Reset - Flexible Threshold (1­-1.3V), Ultra Low Current (100nA) - SilTerra 0.16µm CL160G
  • RAM 8b, 16b, and 32b data widths - TSMC 180nm
    • 8b, 16b, and 32b data widths available.
    • Up to 250MHz clock operation.
    • Read and write data busses may tie for single bus operation.
    • Available production test RTL.
    • VDD 1.6V – 2.0V.
    • Data retention to 0.9V.
    Block Diagram -- RAM 8b, 16b, and 32b data widths - TSMC 180nm
  • XMBus Verification IP
    • Supports XMBus specifications version 0.5.
    • Supports XMBus device types: Master, Slave.
    • Start, repeated start and stop for all possible transfers.
    • Supports 7bit configurable Slave address.
    Block Diagram -- XMBus Verification IP
  • OpenCores Wishbone B3 Verification IP
    • Compliant to OpenCores Wishbone B3 Protocol.
    • Support for all types of Wishbone devices
    • Master
    • Slave
    Block Diagram -- OpenCores Wishbone B3 Verification IP
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