Transform IP

The FFT is factored into Radix-4 Butterfly operations. When an odd power of two is required, a small radix-2 “follower” stage performs the final iteration. The radix-2 stage does not require a full complex rotator so its cost is minimal.
The Radix-4 Engine fetches one complex word of data each clock cycle. Four interleaved data words are collected then applied to the t0-t3 inputs. On successive clock cycles the engine calculates the four frequency domain outputs f0-f3. These are then stored back into the Working Buffer.

This core can perform the two dimensional Discrete Cosine Transform (DCT) and its inverse (IDCT) on an 8x8 block of samples.
The simple, fully synchronous design allows for fast operation while maintaining a low gate count.
It offers high performance and many features to meet your multimedia, digital video and digital printing applications

The eSi-ADAS™ is a suite of radar accelerator IP including a complete Radar co-processor engine, they enhance the overall performance and capabilities of radar systems for automotive, drone and UAV applications that require fast and responsive situational awareness.
The IP has been licensed to some of the leading automotive Tier 1 and Tier 2 suppliers and is in production vehicles.

This macro-cell is an ultra low consumption Power-On Reset (POR) core designed for SilTerra 0.16μm CL160G CMOS technology.
The threshold sensing voltage can be configured from 1V to 1.3V (default is 1.15V). A hysteresis of 120mV is added to avoid false reset glitches in noisy supplies.