Timing-Driven Hybrid RTL/Gate Partitioning for Predictable FPGA-Based Prototyping

Zied Marrakchi, Christophe Alexandre, & Ramsis Farhat, Flexras Technologies
EETimes (3/3/2014 02:30 PM EST)

Software has come to dominate system-on-chip (SoC) development. It is increasingly common for the software effort to be on the critical path of the project schedule. Only FPGA-based prototyping provides both the speed and accuracy necessary to develop and validate complex software integration prior to silicon. The exciting benefits of an FPGA-based prototype are:

• Quick fine tuning of hardware/software integration and software validation pre-silicon
• In-system device validation with real-time interfaces and in end application
• Extended register transfer level (RTL) testing and debugging

Prototyping next-generation SoCs, which contain more functionality than the capacity offered by a single FPGA, means spreading that functionality across multiple FPGAs, leading to challenging partitioning and timing closure issues. Traditional prototyping solutions manage device under test (DUT) partitioning either at the RTL level or at the gate level, but they fail to offer a predictable and efficient flow that would allow the FPGA-based SoC prototype to be brought up quickly.

This post examines FPGA-based prototyping challenges and presents an innovative methodology unifying the benefits of gate-level partitioning and RTL partitioning, providing a short, automated, and predictable path to prototype.

Multi-FPGA partitioning challenges
Multi-FPGA partitioning is a complex optimization problem that must handle multiple constraints and concurrent objectives. The partitioning challenges that have to be overcome to make FPGA-based prototyping effective are:

• Heterogeneous FPGA logic resources management
• Unbalanced interconnect management and pin multiplexing
• Timing closure issues and timing constraints generation
• Incremental flow for fast turnaround
• Full system verification and simulation
• Bug hunting methodologies

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