FPGA-Based Prototyping - "Productivity to Burn"
By Lee Hansen (Xilinx) and Doug Amos (Synplicity)
(01/30/08, 02:02:00 PM EST) -- Programmable Logic DesignLine
These days, a large portion of ASIC, SoC, and ASSP designs are at least partially prototyped in one or more FPGAs. This amounts to many thousands of prototyping projects per year. Compared with other ASIC verification methods, however, FPGA Prototyping is mistakenly seen by many as an ad-hoc mix of tools that must be cobbled together by hand. In reality, powerful integrated tools, platforms, and expertise exist that greatly improve the productivity of FPGA-based ASIC prototyping. This article highlights recent tool advances that can help you set-up, implement, and verify your prototype faster than ever before.
To read the full article, click here
Related Semiconductor IP
- JESD204E Controller IP
- eUSB2V2.0 Controller + PHY IP
- I/O Library with LVDS in SkyWater 90nm
- 50G PON LDPC Encoder/Decoder
- UALink Controller
Related Articles
- A SystemC/TLM based methodology for IP development and FPGA prototyping
- Prototyping Mesh-of-Tree NOC Based MPSOC on Mesh-of-Tree FPGA Devices
- A SystemC based Virtual Prototyping Methodology for Embedded Systems
- FPGA Prototyping of Complex SoCs: RTL code migration and debug strategies
Latest Articles
- Crypto-RV: High-Efficiency FPGA-Based RISC-V Cryptographic Co-Processor for IoT Security
- In-Pipeline Integration of Digital In-Memory-Computing into RISC-V Vector Architecture to Accelerate Deep Learning
- QMC: Efficient SLM Edge Inference via Outlier-Aware Quantization and Emergent Memories Co-Design
- ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design
- COVERT: Trojan Detection in COTS Hardware via Statistical Activation of Microarchitectural Events