FPGA-Based Prototyping - "Productivity to Burn"
By Lee Hansen (Xilinx) and Doug Amos (Synplicity)
(01/30/08, 02:02:00 PM EST) -- Programmable Logic DesignLine
These days, a large portion of ASIC, SoC, and ASSP designs are at least partially prototyped in one or more FPGAs. This amounts to many thousands of prototyping projects per year. Compared with other ASIC verification methods, however, FPGA Prototyping is mistakenly seen by many as an ad-hoc mix of tools that must be cobbled together by hand. In reality, powerful integrated tools, platforms, and expertise exist that greatly improve the productivity of FPGA-based ASIC prototyping. This article highlights recent tool advances that can help you set-up, implement, and verify your prototype faster than ever before.
To read the full article, click here
Related Semiconductor IP
- ReRAM NVM in DB HiTek 130nm BCD
- UFS 5.0 Host Controller IP
- PDM Receiver/PDM-to-PCM Converter
- Voltage and Temperature Sensor with integrated ADC - GlobalFoundries® 22FDX®
- 8MHz / 40MHz Pierce Oscillator - X-FAB XT018-0.18µm
Related Articles
- A SystemC/TLM based methodology for IP development and FPGA prototyping
- Prototyping Mesh-of-Tree NOC Based MPSOC on Mesh-of-Tree FPGA Devices
- A SystemC based Virtual Prototyping Methodology for Embedded Systems
- FPGA Prototyping of Complex SoCs: RTL code migration and debug strategies
Latest Articles
- An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks
- Enabling RISC-V Vector Code Generation in MLIR through Custom xDSL Lowerings
- A Scalable Open-Source QEC System with Sub-Microsecond Decoding-Feedback Latency
- SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks
- An FPGA Implementation of Displacement Vector Search for Intra Pattern Copy in JPEG XS