How designers can survive the embedded multiprocessor revolution
(11/04/07, 09:35:00 PM EST) -- Embedded.com
As Microsoft's Herb Sutter has stated at various occasions - the free lunch is over. On paper the hardware performance improvements continue as normal. To do this, hardware designers, who ran into energy consumption issues a while back, came up with a simple solution and successfully implemented it: instead of increasing clock speed they increased the number of processors.
As a result hardware design can now deliver increased performance based on original roadmap, on first sight satisfying the ever increasing appetite of consumers for more features, more performance at lower cost and lower power consumption.
However, when trying to program these devices, things don't quite add up. Existing, sequential software is unable to unleash the increased performance that the hardware devices offer. Placing software development at a crossroads.
If hardware designers are not able to provide appropriate software development environments that support their devices, the future looks grim. They won't sell any! Without appropriate multiprocessor software development environments programmers will be left out in the cold and will not be able to leverage additional performance offered by Multiprocessor System-on Chips (MPSoCs)
To read the full article, click here
Related Semiconductor IP
- Sine Wave Frequency Generator
- CAN XL Verification IP
- Rad-Hard GPIO, ODIO & LVDS in SkyWater 90nm
- 1.22V/1uA Reference voltage and current source
- 1.2V SLVS Transceiver in UMC 110nm
Related White Papers
- System configurations for power systems based on PMBus 1.3
- Interstellar: Fully Partitioned and Efficient Security Monitoring Hardware Near a Processor Core for Protecting Systems against Attacks on Privileged Software
- Embedded Symmetric MultiProcessing system on a SoC with 1.6GHz PowerPC IP in 45nm
- Chips in Space -- MacSpace, A Record Throughput Multi-Core Processor for Satellites
Latest White Papers
- OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs
- Balancing Power and Performance With Task Dependencies in Multi-Core Systems
- LLM Inference with Codebook-based Q4X Quantization using the Llama.cpp Framework on RISC-V Vector CPUs
- PCIe 5.0: The universal high-speed interconnect for High Bandwidth and Low Latency Applications Design Challenges & Solutions
- Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS