FPGA partial reconfiguration mitigates variability
(04/03/2006 9:00 AM EDT), EE Times
Design variability is rapidly becoming the “norm” for electronics products. From packaging to logic functionality, electronic end products are expected to be more customized and configurable based on customer demand and field environment.
For logic design, this means the hardware must be able to handle a variety of functions, which leads to more devices and more real estate. A common method to handle this additional functionality has been to move them into switchable software modules handled by a microprocessor. However, a growing number of applications are relying on FPGA-based partial reconfiguration technology to leave logic functions in hardware, switch them in and out on demand — all while leaving your core logic running.
To read the full article, click here
Related Semiconductor IP
- Post-Quantum Digital Signature IP Core
- Compact Embedded RISC-V Processor
- Power-OK Monitor
- RISC-V-Based, Open Source AI Accelerator for the Edge
- Securyzr™ neo Core Platform
Related White Papers
- Partial reconfiguration in FPGA rapid prototyping tools
- An MDE Approach For Implementing Partial Dynamic Reconfiguration In FPGAs
- Accelerate partial reconfiguration with a 100% hardware solution
- Accelerating Architecture Exploration for FPGA Selection and System Design
Latest White Papers
- DRsam: Detection of Fault-Based Microarchitectural Side-Channel Attacks in RISC-V Using Statistical Preprocessing and Association Rule Mining
- ShuffleV: A Microarchitectural Defense Strategy against Electromagnetic Side-Channel Attacks in Microprocessors
- Practical Considerations of LDPC Decoder Design in Communications Systems
- A Direct Memory Access Controller (DMAC) for Irregular Data Transfers on RISC-V Linux Systems
- A logically correct SoC design isn’t an optimized design