Slash SoC power consumption in the interconnect

Jonah Probell (Arteris)
EDN - November 24, 2014

A modular approach to SoC interconnect slashes power consumption with unit-level clock gating.

While power management has only grown in importance for system-on-chip (SoC) developers, the one crucial area that is often overlooked is the interconnect. While most power management efforts focus on the computational aspects of the SoC, designers who adopt a more modular interconnect could reduce die size, alleviate routing congestion, and, by doing so, cut overall chip power consumption by as much as 0.7 milliwatts. A reduction this significant could be a game-changer in next-generation systems for mobility and power-conscious data center applications.

The modular concept is different from other types of interconnects because it consists of a distributed architecture of switches, buffers, firewalls, pipe stages, and clock and power domain crossings. By using a universal transport protocol between all of the separate units on the chip, the modular approach enables designers to implement unit level clock gating to eliminate clock tree switching power where no traffic is present.

Modular on-chip network-on-chip (NoC) technology also reduces power consumption by localizing logic, minimizing long wires, and keeping capacitance low. Designers who want to further enhance the power management abilities of their SoC design can explore measures to reduce the area and leakage power consumption of the chip by using the simplicity of a NoC transport protocol to serialize data paths and thereby minimize logic.

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