High speed NoC (Network On-Chip) Interconnect IP

Overview

The ORBIT On-Chip Interconnect (OIC) delivers exceptional performance, and SoC design flexibility based on automated end-to-end interconnect generation flow. It enables high-speed routing with pre-calculated routing path details and supports higher speed, low latency, and floorplan flexibility.

Key Features

Memory Subsystem IP
- Tuning the performance for the entire SoC memory subsystem
- ActiveQoS bandwidth and latency control for the entire SoC memory subsystem
High-Speed HyperPath Technology
- More than 1GHz at 28nm processor or more than 800MHz at low power 28nm
Flexible Floorplan & Physical Design Friendly
- Long-distance Asynchronous Bridge (LDA) technology solves long and narrow topology design
Ultra Low Power
- Enables <200uW idle power for entire backbone (+3M gate size)
Area (Wire Congestion)
- Less than 50% of typical AXI-based backbone bus area
Design Tools
- End-to-end RTL and verification package generation with ORBIT toolkit

Benefits

High Performance
- Proprietary HyperPath technology enabling 2x performance
- Extremely low latency with LDA technology
- Dynamic priority control in OIC and OMC, based on observed latency & bandwidth (ActiveQoS)
Low Power Consumption
- Advanced Clocking enables extremely low power
- Proactively clock-gating
High Flexibility
- Automated end-to-end RTL generation with an ORBIT design toolkit
- Fast & easy SoC design of high-speed and long-distance interconnect
Safety & Security
- End-to-end ECC (SECDED) support
- End-to-end at-speed BIST

Block Diagram

Applications

Automotive,
Application Processors,
Digital Baseband Modems,
Set-Top-Box,
Digital TV,
OTT,
Surveillance,
IoT,
Enterprise SSD Controllers

Deliverables

IP Core RTL
Simulation Environment
Synthesis, Lint Script
Detail Documentation

Technical Specifications

Maturity

Silicon Proven & Market Proven

Availability

Now

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