High speed NoC (Network On-Chip) Interconnect IP

Overview

OPENEDGES is the only total memory system IP company providing both memory controller and on-chip interconnect. OIC is the ORBIT high-speed On-chip Interconnect, which delivers exceptional performance and SoC design flexibility based on automated end-to-end interconnect generation flow. Together with ORBIT Memory Controller (OMC), OIC delivers significant synergy in terms of maximum performance, reduced SoC design efforts, and a lot easier post-silicon debugging/tuning.

Today’s SoC gets increasingly complex and performance-demanding with multi-core & multiple DRAM channels. Conventional crossbar-based bus design fails to meet these requirements, significantly increasing overall SoC design efforts. OIC is the next-generation high-speed interconnect IP, which features high performance, small area & ultra-low power consumption through proprietary HyperPath technology and proprietary Asynchronous Bridge technology. With these proven & unique technologies, OIC enables customers to reduce SoC’s backbone area (& global wires) by almost half while satisfying SoC’s high bandwidth and low latency demand. OIC’s automated end-to-end interconnect generation flow provides SoC design flexibility, significantly reducing SoC design efforts.

Key Features

High Performance
- Proprietary HyperPath technology enabling 2x data-path speed over conventional bus design
- Proprietary Asynchronous Bridge design enabling low latency and high-speed implementation
Low Power Consumption
- Extremely low power consumption – 10’s to 100’s uW for the entire backbone at idle
Smaller Area
- Lightweight NoC enabling smaller interconnect channel area – 1/2x of typical AMBA-based interconnect area
Special Features
- Centralized clock & power management support
- ECC (SECDED) support for error resilience
- End-to-end at-speed BIST
- Performance (e.g., bandwidth, latency) monitors

Benefits

High Flexibility
- Flexibility for easy SoC floorplan & topology design
- Automated end-to-end interconnect generation with ORBITTM Design Toolkit
Physical-design friendliness
- Fast & Easy SoC design of high speed & long distance interconnect
Easy power & clock management
- Integrated local CMU/PMU abstracting out complex internal handshake (OIC+OMC) for power & clock control
- Externally, AMBA Low Power Interface (P channel)
Easy post-silicon performance tuning
- Dynamic priority control in OIC & OMC based on observed latency & bandwidth for master IPs (ActiveQoSTM)

Block Diagram

Applications

Automotive,
Application Processors,
Digital Baseband Modems,
Set-Top-Box,
Digital TV,
OTT,
Surveillance,
IoT,
Enterprise SSD Controllers

Deliverables

IP Core
Management SW
Simulation environment
Detailed Document

Technical Specifications

Maturity

Silicon Proven & Market Proven

Availability

Now

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