Hard IP too costly to use just once

Hard IP too costly to use just once
By Mahendra Jain, EE Times
January 18, 2000 (11:49 a.m. EST)
URL: http://www.eetimes.com/story/OEG20000118S0024

Electronics companies are turning to design reuse as a practical means of staying competitive and as a way to implement system-on-chip (SoC) design. Reusing existing intellectual property (IP) allows companies to solve mission-critical issues that range from scarcity of resources and inadequate design environments to time-to-market pressures and product differentiation.

Most of today's industry discussion centers on the reuse of soft IP. The majority of available IP, however, is hard IP-that is, designs represented as mask layouts. Every year, semiconductor companies spend billions of dollars designing hard IP. Most of it is never used more than once.

While hard IP is not being fully utilized, the industry stays focused on soft IP, perhaps because it is perceived as easier to modify-and easier to understand. Sagantec contends that hard IP offers an attractive return on investment for SoC design and implementation.

As preverifie d and synthesized software blocks, soft IP offers flexibility, but needs to be functionally verified. Though easily modified, it requires re-placement and rerouting at the layout level, the equivalent of a complete redesign and a new silicon verification cycle. Hard IP is any IP verified in silicon and available as a physical layout in GDSII format. ARM, MIPS and Rambus IP are available in hard form. The majority of processors, digital signal processors, analog functions and basic foundation libraries are only available as hard IP Hard IP can be reused for next-generation technology and can be migrated to different fabs with ease using physical-design migration software.

The reuse of hard IP and the ability to optimize it directly at the layout level ensures that designs are completed faster. Hard-IP reuse can accelerate a product's time-to-market by reusing or migrating a cell library or a block from an old design into a new one.

Migration for second-sourcing is popular among fabless semic onductor companies that try not to be dependent on one silicon vendor.

There are numerous advantages of reuse at the layout level. Designers are working from a design that's already proven in silicon. Timing and functionality are known, characterized and based on a particular process technology. As a result, the verification time is shorter, while the rate of success is high.

As the industry moves to small geometries, more time will be spent in the layout phase accounting for electromigration, power, crosstalk and signal integrity. It would be a waste of valuable design investment not to reuse existing layouts.

As SoC becomes more mainstream, the focus must shift to hard-IP reuse. Semiconductor companies are creating organizations to coordinate and reuse existing hard IP, and developing new hard IP with the goal of reuse. Designers are relearning the way they do integrated-circuit design to leverage the integration capabilities offered by the deep-submicron semiconductor technology.

To stay competitive in the marketplace, design reuse is inevitable. Reusing hard IP is proving to be a key element of a design reuse methodology and a viable SoC implementation plan.

Mahendra Jain is Vice President of Worldwide Marketing at Sagantec (Fremont, Calif.).