Sidense OTP Memory IP Enables 65nm Mobile Handset Chip

• High-density memory macro helps ParkerVision meet power, cost and form factor constraints
• Qualified, embedded non-volatile memory (NVM) technology available at multiple foundries

– Sidense, a leading developer of Logic Non-Volatile Memory (LNVM) IP cores, today announced that its 1T-OTP one-time programmable (OTP) memory IP is available for customer designs at the 65nm process node.  Sidense is the first embedded OTP vendor to announce high density (above 1 Mbit) product availability for both standard-logic and low-power 65nm implementation.

Sidense’s OTP memory was selected for use in ParkerVision’s 65nm d2p mobile handset solution.  “ParkerVision selected the SiPROM architecture for its small size, low power, and speed of programming.  We had need for onboard memory and wanted to add some programmability for future features without compromising on our existing size and cost targets.   Because our product is used in mobile handsets, power and form factor are paramount,” said Domingo Figueredo, VP of Engineering at ParkerVision.  “The excellent support received from Sidense has helped us realize first-pass silicon success,” he added.

 “The low power, small footprint and high security of our 1T-OTP technology provide our customers with embedded non-volatile memory arrays that give them competitive cost and performance advantages,” said Xerxes Wania, Sidense President and CEO.  “In addition, our silicon-proven, ‘foundry friendly’ OTP lets designers choose from a wide range of foundries and processes for implementing their devices.”

Sidense SiPROM NVM arrays, based on the Company’s patented 1T-Fuse™ technology, have been silicon proven in 65nm for both standard-logic and low-power processes and are available in densities up to 8 Mbits.  Memory arrays are available from 180nm down to 55nm at many popular foundries.

About Sidense

Sidense Corp., the only logic non-volatile memory provider listed on EE Times 60 Emerging Startups list for 2009, provides secure, dense and reliable non-volatile, one-time programmable (OTP) memory IP for use in standard-logic CMOS processes, with no additional masks or process steps required.  Sidense's patented one-transistor 1T-Fuse™ architecture (U.S. Patent #7402855 and others) provides the industry’s smallest footprint and lowest power Logic Non-Volatile Memory (NVM) solution.

Sidense OTP memory is available at 180nm, 130nm, 110nm, 90nm, 65nm, and 55nm and is scalable to 40nm and below.  The IP is available at UMC, TSMC, SMIC, Tower, Fujitsu Microelectronics, IBM and Chartered.  Customers are using Sidense OTP for analog trimming, code storage, encryption keys such as HDCP, RFID and Chip ID, medical, automotive, and configurable processors and logic.  For more information, visit www.sidense.com.