OTP IP
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1,121
IP
from 14 vendors
(1
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10)
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A 180nm Flip-Chip IO library with 1.2-1.8V GPIO, 1.8V & 5V analog/RF, 20-36V ultra-low leakage low-cap HV analog and OTP program cell
- GPIO:
- ANALOG
- OTP Programming Cell
- Physical Attributes
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A 130nm Wirebond IO library with 3.3V GPIO, LVDS TX & RX, 3.3V I2C open-drain, analog cell and OTP program cell
- GPIO:
- I2C / SMBUS Open-Drain I/O:
- LVDS
- ANALOG
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A 65nm Wirebond IO library with 1-3.3V GPIO, 3.3V pulse-width modulation cell, I2C & SVID open-drain, 3.3V & 5V analog and OTP program cell
- GPIO:
- I2C / SVID Open-Drain I/O:
- ANALOG
- OTP Programming Cell
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28nm Wirebond IO library with dynamically switchable 1.8V/ 3.3V GPIO, 5V I2C open-drain, 1.8V & 3.3V analog, OTP program cell, and HDMI & LVDS protection macros - featured across a variety of metal stack and pad configuration options
- General-Purpose IO
- I2C/SMBUS Open Drain I/O
- ANALOG
- HDMI & LVDS protection Macros
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OTP
- Bit Cell Structure : 0.5 Transistor based
- Bit Cell Size : 7.5F2
- Bit Cell Process : Standard CMOS Logic Process plus one extra mask
- On-chip Capacity : Up to 256Mb beyond 4Mb Scalable to 20 nm node and below
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512x8 Bits OTP (One-Time Programmable) IP, TSMC 12FFC 0.8V/1.8V Process
- Fully compatible with TSMC 12FFC 0.8V/1.8V
- Low voltage: 0.8 V ± 10% for read and 1.1 V ± 5% for program
- High speed: 10µs program time per bit, and 50ns read 8-bit at a time
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4Kx16 Bits OTP (One-Time Programmable) IP, UMC 110 nm 1.2V/3.3V L110AE Process
- Fully compatible with UMC Logic/Mixed-Mode 110nm Aluminum Enhancement CMOS process
- Low voltage: 1.2 V ± 10% read voltage, 3.8 V ± 5% program voltage
- High speed: 10-µs program time per bit
- Wide temperature: -40°C to 125°C read and 10°C to 40°C program