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Compare 9 IP from 7 vendors (1 - 9)
  • Heterogeneous eFPGA architecture with LUTs, DSPs, and BRAMs on GlobalFoundries GF12LP
    • An experimental Z1010 heterogeneous eFPGA architecture with LUTs, DSPs, and BRAMs has been ported to the GlobalFoundries GF12LP process.
    • The picture below shows the full layout of the experimental architecture. The official Z1010 standard will include a different ratio of LUTs, DSPs, and BRAM.
    Block Diagram -- Heterogeneous eFPGA architecture with LUTs, DSPs, and BRAMs on GlobalFoundries GF12LP
  • eFPGA on GlobalFoundries GF12LP
    • All Platypus eFPGA hardened IP cores are backed up by an open architecture guarantee. Complete machine readable descriptions of standard architectures can be found in the Logiklib open source repository.
    • The Z1000 standard eFPGA architecture has been ported to the GlobalFoundries GF12LP process.
    Block Diagram -- eFPGA on GlobalFoundries GF12LP
  • eFPGA Hard IP Generator
    • Combination of over 30 years of programmable logic experience and expertise with proven standard ASIC design methodologies to create an eFPGA IP generator that can create and deliver a domain-specific eFPGA IP in as little as four weeks.
    Block Diagram -- eFPGA Hard IP Generator
  • eFPGA
    • Customize Vega to suit your needs
    • Accelerate your processor with Vega eFPGA
    • Seamlessly integrate and verify Vega IP into your SoC design
    • Enhance flexibility with on-chip FPGA functionality
    Block Diagram -- eFPGA
  • Radiation-Hardened eFPGA
    • Radiation-Hardened by Design (RHBD): Built to operate in space and defense applications, ensuring reliability under extreme conditions.
    • Customizable eFPGA IP: Tailored to specific mission requirements with adaptability to various process nodes and foundries.
    • High Reliability: Designed to withstand Total Ionizing Dose (TID) and Single Event Effects (SEE).
  • eFPGA Soft IP
    • These eFPGA IP cores offer designers the flexibility to tailor resources to their application requirements, available as either Soft RTL or Hard GDSII IP.
    • Our standard-cell-based approach facilitates rapid porting to new process geometries or variants, including industrial and rad-hard grade versions.
    Block Diagram -- eFPGA Soft IP
  • Embedded FPGA
    • Speedcore embedded FPGA (eFPGA) IP has brought the performance and flexibility of programmable logic to ASICs and SoCs.
    • Customers can integrate a Speedcore eFPGA IP into an ASIC or SoC for high-performance, compute-intensive and real-time processing applications such as artificial intelligence (AI), machine learning (ML), 5G wireless, networking, storage and automotive.
    Block Diagram -- Embedded FPGA
  • Embedded FPGA
    • Fully integrated into RTL SOC design flow
    • Highly scalable and customizable
    • Technology independent
    Block Diagram -- Embedded FPGA
  • XAUI 10Gb Ethernet Attachment Unit Interface
    • XAUI compliant functionality supported by embedded SERDES PCS functionality implemented in the LatticeECP2M and LatticeECP3, including four channels of 3.125 Gbps serializer/deserializer with 8b10b encoding/decoding.
    • Complete 10Gb Ethernet Extended Sublayer (XGXS) solution based on LatticeECP2M and LatticeECP3 FPGA.
    • Soft IP targeted to the FPGA implements XGXS functionality conforming to IEEE 802.3ae-2002, including:
    • Aldec and ModelSim simulation models and test benches provided for free evaluation.
    Block Diagram -- XAUI 10Gb Ethernet Attachment Unit Interface
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Semiconductor IP