Speedcore eFPGA IP brings the power and flexibility of programmable logic to ASICs and SoCs. Customers specify their logic, RAM, MLP and DSP resource needs, then Achronix configures the Speedcore IP to meet their individual requirements. Speedcore look-up-tables (LUTs), RAM, MLP and DSP64 blocks can be assembled like building blocks to create the optimal programmable fabric for any given application. A personalized version of the ACE design tools to program the Speedcore IP is included with the Speedcore IP delivery.
Speedcore eFPGA technology has been in production and shipping to end customers since 2016. Achronix’s customers include some of largest technology companies in the world. These companies have recognized that Speedcore IP is disruptive technology that allows them to dramatically increase the overall performance of their systems.
Embedded FPGA
Overview
Key Features
- Speedcore™ Embedded FPGA (eFPGA) IP – The only eFPGA technology shipping in high-volume production applications:
- Customer-defined eFPGA resource counts for logic, embedded memory blocks, MLP and DSP blocks
- Logic – 6-input look-up-tables (LUTs) plus integrated wide MUX functions and fast adders
- Logic RAM – 2 kb per memory block for LRAM2k, and 4kb per memory block for LRAM4k
- Block RAM – 72 kb per memory block for BRAM72k, and 20kb per memory block for BRAM20k
- DSP64 – 18 × 27 multiplier, 64-bit accumulator and 27-bit pre-adder per block
- Machine learning processors (MLP) – 32 multiplier/ accumulators (MACs) per block, supporting integer and floating point formats
- Achronix delivers the eFPGA IP as a hard macro in GDSII format.
- Speedcore IP is available on the following process technology nodes:
- TSMC 16FF+
- TSMC 7nm FinFET
- TSMC 12FFC under development
- Speedcore IP can be ported to other process nodes
- Speedcore performance:
- Max: 750 MHz
- Typical: 300 MHz to 500 MHz
- Lowest latency interface:
- One stage of latency between a Speedcore instance and the host SoC
- Support for zero-latency interfaces
- Speedcore IP supported by Achronix ACE design tools:
- Full-featured tools to synthesize, place, route and optimize performance for RTL targeting a Speedcore eFPGA
- Includes Synplify Pro for synthesis
- Easy evaluation:
- Benchmark designs using Achronix ACE design tools
- Verify functionality using the VectorPath™ accelerator card
Benefits
- 75% lower power
- 90% lower cost
- 100× lower latency
- 10× higher bandwidth
Block Diagram
Video
Supercharge your ASICs and SOCs with the industry’s only silicon-proven embedded FPGA technology.
Technical Specifications
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