All Platypus eFPGA hardened IP cores are backed up by an open architecture guarantee. Complete machine readable descriptions of standard architectures can be found in the Logiklib open source repository.
Parametrized soft RTL logic wrap the hardened IP core to handle reset, boot-up, security, and bitstream loading. Bitstream programming is done via a standardize memory mapped register interfaces (APB, AXI-Lite, or UMI) selectable by the user during design integration.
The Z1000 standard eFPGA architecture has been ported to the GlobalFoundries GF12LP process. The picture below shows the full layout (GDS) of an integration ready Z1000 eFPGA core.
| Process | LUTs | Regs | I/O | DSPs | BRAM | Width | Height |
|---|---|---|---|---|---|---|---|
| GF12LP | 2,048 | 2,048 | 1,024 | 0 | 0 | 1036.8um | 1037.2um |
