eFPGA Soft IP

Overview

Key Features

• Higher Performance of eFPGA Soft IP: With Menta eFPGA, concerns regarding board-space, I/O latency, and bandwidth are alleviated as accelerators are brought on-chip, eliminating limitations and overhead associated with I/O pad count or chip-to-chip communication interfaces.
• eFPGA Means Lower Power Consumption: In a COT FPGA, all the extra to the programmable logic, such as high-speed interfaces, PLL, and controllers consume around half of the power. All our power saving advances lead an algorithm on a Menta eFPGA IP to consume between 10 and 50% of the power of the same algorithm on a FPGA.
• Design Insurance with Menta eFPGA: To maximize flexibility, it's crucial to prioritize process-portability. Menta eFPGA stands out as the sole 100% standard-cell-based solution, facilitating rapid porting of your eFPGA to any new process geometry or variant of your choice. This is achieved using the same automated, standard EDA flow as for the rest of your SoC. Leveraging our industry gold-standard Synopsys-based implementation flow, Menta ensures portability within mere weeks, empowering you to adapt swiftly to evolving technological landscapes.
• Security with eFPGA Soft IP: In today’s global design chain, protecting intellectual property (IP) and trade secrets is increasingly vital. Menta eFPGA allows you to delay delivering proprietary technology to end customers until it is delivered as a field-upgrade, minimizing the chance for competitors to reverse engineer your product. This strategic approach enhances security and preserves valuable IP throughout the product lifecycle.
• Protection of Industrial Intellectual Property: With Menta eFPGA, you can securely deliver your proprietary technology to end customers through field-upgrade capabilities, significantly reducing the risk of competitors reverse-engineering your product.
• Reduction of Costs Thanks to eFPGA: As production volumes increase, onboard FPGAs can rapidly become financially impractical. With Menta eFPGA, you can seamlessly integrate FPGA functionality directly onto the chip, effectively reducing manufacturing cost up to 85% and conserving valuable board space, all while ensuring full field-upgradability.
• Higher Performance of eFPGA Soft IP: With Menta eFPGA, concerns regarding board-space, I/O latency, and bandwidth are alleviated as accelerators are brought on-chip, eliminating limitations and overhead associated with I/O pad count or chip-to-chip communication interfaces.
• eFPGA Means Lower Power Consumption: In a COT FPGA, all the extra to the programmable logic, such as high-speed interfaces, PLL, and controllers consume around half of the power. All our power saving advances lead an algorithm on a Menta eFPGA IP to consume between 10 and 50% of the power of the same algorithm on a FPGA.
• Design Insurance with Menta eFPGA: To maximize flexibility, it's crucial to prioritize process-portability. Menta eFPGA stands out as the sole 100% standard-cell-based solution, facilitating rapid porting of your eFPGA to any new process geometry or variant of your choice. This is achieved using the same automated, standard EDA flow as for the rest of your SoC. Leveraging our industry gold-standard Synopsys-based implementation flow, Menta ensures portability within mere weeks, empowering you to adapt swiftly to evolving technological landscapes.
• Security with eFPGA Soft IP: In today’s global design chain, protecting intellectual property (IP) and trade secrets is increasingly vital. Menta eFPGA allows you to delay delivering proprietary technology to end customers until it is delivered as a field-upgrade, minimizing the chance for competitors to reverse engineer your product. This strategic approach enhances security and preserves valuable IP throughout the product lifecycle.
• Protection of Industrial Intellectual Property: With Menta eFPGA, you can securely deliver your proprietary technology to end customers through field-upgrade capabilities, significantly reducing the risk of competitors reverse-engineering your product.
• Reduction of Costs Thanks to eFPGA: As production volumes increase, onboard FPGAs can rapidly become financially impractical. With Menta eFPGA, you can seamlessly integrate FPGA functionality directly onto the chip, effectively reducing manufacturing cost up to 85% and conserving valuable board space, all while ensuring full field-upgradability.
• Higher Performance of eFPGA Soft IP: With Menta eFPGA, concerns regarding board-space, I/O latency, and bandwidth are alleviated as accelerators are brought on-chip, eliminating limitations and overhead associated with I/O pad count or chip-to-chip communication interfaces.
• eFPGA Means Lower Power Consumption: In a COT FPGA, all the extra to the programmable logic, such as high-speed interfaces, PLL, and controllers consume around half of the power. All our power saving advances lead an algorithm on a Menta eFPGA IP to consume between 10 and 50% of the power of the same algorithm on a FPGA.

Benefits

• HIGHLY DESIGN ADAPTIVE IP
• Support of any technology node, foundry and process option
• High LUTs density
• Support of any kind of arithmetic block right within the IP
• Support of any type and amount of memories, right within the IP
• Specific IP specification software available to help defiing the perfect IP for customer SoC and application (Origami Designer)
• ASIC like options: power management
• Can be rad-hard by design
• EASIEST SOC INTEGRATION
• No specific interface
• Highest yield and reliability
• Best testability and cost (TC & FC of 99.7%+). Standard scan chain
• Best and simplest verification flow
• No change in customer EDA flow. No extra software required
• BEST USABILITY
• State of the art programming software (Origami Programmer)
• Several distribution models possible
• No export restrictions

Block Diagram

Applications

• Aerospace & Defence
• Cryptography
• Motor Controls
• Adaptive Data conversion
• Avoid trojan/hacking at Foundry
• Automotive
• Autonomous driving - AI for vision applications
• Security algorithms over lifetime
• Checker and voting logic for lock-steps mode
• Motor controls
• Battery monitoring systems
• HPC / Networking / 5G
• AI learning accelerator
• Cryptography accelerators
• 5G base stations evolving standards
• Post production customizable CPU
• SSD controller
• Risk reduction
• IoT / IIoT
• AI inference at the edge
• System time to market and cost reduction
• Reduction of variants

Deliverables

• Origami Programmer software
• GDSII and all files necessary for integration, verification, simulation and test
• Datasheets, documention
• Can deliver on any CMOS process at any foundry.
• Off the shelf IPs available on XFAB XH018 (rad-hard), STM 28FDSOI, GF12LP and TSMC 12FFC.

Technical Specifications