Australis is the combination of over 30 years of programmable logic experience and expertise with proven standard ASIC design methodologies to create an eFPGA IP generator that can create and deliver a domain-specific eFPGA IP in as little as four weeks.
eFPGA Hard IP Generator
Overview
Key Features
- Bespoke
- Highly customizable, from the right amount of LUT6s, BRAMs and DSP blocks, routing channels to different transistor options
- Proven
- eFPGA IP is generated with proven standard cell ASIC libraries for the chosen process node / foundry combination
- Specialized
- Can be implemented utilizing specialized cell libraries, such as RHBD or automotive qualified libraries
- Secure
- With different options to secure the eFPGA bitstream, we have a security option that keeps your device secure
- Reconfigurable
- Adapt to evolving market needs and extend the longevity and usefulness of your SoC
- Optimized
- To meet your specific performance, power consumption and area requirements
Benefits
- Customization
- eFPGA IP can be generated and customized to any foundry/process technology within days for supported processes and within a quarter for new technologies.
- Fast Time-to-Market
- No fixed arrays, providing complete freedom to design your core exactly as needed for rapid deployment.
- Versatility
- Specify the number of DSP, LUT, and BRAM columns, define X/Y array size, and customize column placement to meet your specific design requirements.
- Cost-Effective
- Automated core customization reduces both costs and time, enabling more efficient project delivery.
- Radiation-Hardened Options
- Generate eFPGA IP using Radiation-Hardened By Design (RHBD) standard cell libraries to meet stringent radiation effect requirements.
- Reliable Performance
- Enjoy peace of mind with low risk eFPGA solutions designed to work seamlessly in your applications.
Block Diagram
