10Gb Ethernet Attachment Unit Interface or XAUI is a high-speed interconnect that offers reduced pin count and has the ability to drive up to 20 inches of PCB trace on standard FR-4 material. Each XAUI interface comprises four self-timed 8b10b encoded serial lanes each operating at 3.125 Gbps and thus is capable of transferring data at an aggregate rate of 10 Gbps.
XAUI IP Core provides a solution for bridging between XAUI and 10 Gigabit Media Independent Interface (XGMII) devices. This IP core implements 10Gb Ethernet Extended Sublayer (XGXS) capabilities in soft logic that together with PCS and SERDES functions implemented in the FGPA provides a complete XAUI-to-XGMII solution.
XAUI 10Gb Ethernet Attachment Unit Interface
Overview
Key Features
- XAUI compliant functionality supported by embedded SERDES PCS functionality implemented in the LatticeECP2M and LatticeECP3, including four channels of 3.125 Gbps serializer/deserializer with 8b10b encoding/decoding.
- Complete 10Gb Ethernet Extended Sublayer (XGXS) solution based on LatticeECP2M and LatticeECP3 FPGA.
- Soft IP targeted to the FPGA implements XGXS functionality conforming to IEEE 802.3ae-2002, including:
- 10 GbE Media Independent Interface (XGMII).
- Optional Slip buffers for clock domain transfer to/from the XGMII interface.
- Complete translation between XGMII and XAUI PCS layers, including 8b10b encoding and decoding of Idle, Start, Terminate, Error and Sequence code groups and sequences, and randomized Idle generation in the XAUI transmit direction.
- XAUI compliant lane-by-lane synchronization.
- Lane deskew functionality.
- Interface with the high-speed SERDES block embedded in the LatticeECP2M and LatticeECP3 that implements a standard XAUI.
- Optional standard compliant MDIO/MDC interface.
- Aldec and ModelSim simulation models and test benches provided for free evaluation.
Block Diagram
