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DO254 IP

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Compare 84 IP from 12 vendors (1 - 10)
  • DO-254 compliant MIL-STD-1553B IP core
    • 64K bytes internal static RAM with RAM Error Detection/Correction option
    • 16-bit time tag counters and clock sources for all terminals
    Block Diagram -- DO-254 compliant MIL-STD-1553B IP core
  • CAN ARINC 825 - DO-254
    • IP developed according to DO-254/ED-80 guidance. Compliant DAL A.
    • Compliant with ARINC825-1 Specification. May 10, 2010.
    • Compliant with CAN 2.0 Specification (v 2.0) published by Bosh (part A and part B).
    • Able to recover from SEU (self healing feature) and to report any detected errors thanks to its embedded reliability features.
    Block Diagram -- CAN ARINC 825 - DO-254
  • DO-254 CAN FD Controller
    • Design Assurance Level A according to RTCA DO-254/ED-80 (April, 2000)
    • Fully compliant to ISO 11898-1:2015
    • Supports both Classical and Flexible Data Rate frame formats
    • Tested as specified in the ISO 16845-1:2016
    Block Diagram -- DO-254 CAN FD Controller
  • DO-254 UART
    • Design Assurance Level A according to RTCA DO-254/ED-80 (April, 2000)
    • Configurable baud rate, number of data bits, parity and stop bits.
    • Fully deterministic handshake interface that allows easy handling of reception/transmission requests
    • Single clock domain fully synchronous design
    Block Diagram -- DO-254 UART
  • DO-254 SPI Slave
    • Design Assurance Level A according to RTCA DO-254/ED-80 (April, 2000)
    • Fully compliant to the SPI Standard (Motorola’s M68H11 Reference Manual)
    • Automatically detects and adjusts to the bus data rate
    • Configurable phase, polarity and word size
    Block Diagram -- DO-254 SPI Slave
  • DO-254 SPI Master
    • Design Assurance Level A according to RTCA DO-254/ED-80 (April, 2000)
    • Fully compliant to the SPI Standard (Motorola’s M68H11 Reference Manual)
    • Configurable data rate
    • Configurable phase, polarity and word size
    Block Diagram -- DO-254 SPI Master
  • DO-254 SDRAM Controller
    • Design Assurance Level A according to RTCA DO-254/ED-80 (April, 2000)
    • Compliant to JEDEC Standard No. 21-C Page 3.11.5.1 Release 12
    • Single clock domain fully synchronous design
    • Configurable to support any SDRAM device
    Block Diagram -- DO-254 SDRAM Controller
  • DO-254 I2C Slave
    • Design Assurance Level A according to RTCA DO-254/ED-80 (April, 2000)
    • Fully compliant to the I2C-bus specification and user manual Rev. 5 – 9 October 2012 for Standard-mode, Fast-mode and Fast-mode Plus (Fm+)
    • Configurable data rate (100kHz, 400kHz or 1000kHz)
    • Support for all Options (Multi-master, Synchronization, Arbitration, Clock stretching, 10-bit slave address, General Call address, Software Reset and START byte)
    Block Diagram -- DO-254 I2C Slave
  • DO-254 I2C Master
    • Design Assurance Level A according to RTCA DO-254/ED-80 (April, 2000)
    • Fully compliant to the I2C-bus specification and user manual Rev. 5 – 9 October 2012 for Standard-mode, Fast-mode and Fast-mode Plus (Fm+)
    • Configurable data rate (100kHz, 400kHz or 1000kHz)
    • Support for all Options (Multi-master, Synchronization, Arbitration, Clock stretching, 10-bit slave address, General Call address, Software Reset and START byte)
    Block Diagram -- DO-254 I2C Master
  • DO-254 ARINC-429 Transmitter
    • Compliant to ARINC Specification 429-17 (May 17, 2004)
    • Design Assurance Level A according to DO-254 / ED-80
    • Single clock domain fully synchronous design
    • Configurable data rate
    Block Diagram -- DO-254 ARINC-429 Transmitter
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