I2C Master DO-254 IP Core

Overview

The I2C Master IP Core implements an I2C Master fully compliant to the I2C-bus specification and user manual Rev. 5 – 9 October 2012 for Standard-mode, Fast-mode and Fast-mode Plus (Fm+).

The Inter-Integrated Circuit (I2C) is a multi-master, multi-slave, single-ended, serial computer bus invented by Philips Semiconductor (now NXP Semiconductors). The I2C bus is typically used for attaching lower-speed peripheral ICs to processors and microcontrollers.

The I2C Master IP Core has been developed to DAL A according to the DO-254 / ED-80 and is accompanied by a Certification Kit. For lower DAL levels reduced documentation sets are available. The core is also available as a netlist for DAL D or projects not needing the full RTL source.

Safe Core Devices provides two separate IP Cores, one for the I2C Master IP Core and one for the I2C Slave IP Core. If the system needs to be capable of transmitting and receiving both cores can be instantiated in the target device.

Implementation Details

Unless otherwise specified all the runs have been performed with the default options of the respective tool. Register placement on the IO has been disabled.

No constraints were added, so the results listed under the column “Maximum frequency of operation” are the worst case scenario (no multicycle, false paths, etc. defined).

The results are provided for an I2C Master Core with g_SCL_DIVIDER = 16 and without TMR (Triple Module Redundancy), if TMR is used the number of registers will be triplicated, the combinatorial logic will also increase and there might be a penalty on the maximum ‘clk’ frequency.

Note: The results provided below are for some arbitrarily selected devices. If a device does not appear in a table below it does not mean that it is not supported. The I2C Master Core can be implemented in any technology.

ACTEL/MICROSEMI

FPGA Type Maximum ‘clk‘ Frequency Logic Modules (CORE)
ProASIC3

 

(A3P015 68QFN I Std)

123 MHz 205
IGLOO

 

(AGL030V5 100VQPF I Std)

112 MHz 197
Fusion

 

(AFS090 180QFN I Std)

123 MHz 205
Axcelerator

 

(RTAX250S 208CQFP Mil Std)

135 MHz SEQUENTIAL (R-cells): 52

 

COMB (C-cells): 75

ALTERA

FPGA Type Maximum ‘clk’ Frequency Flip-Flops ALUTs ALMs Logic Cells
MAX II

 

(EPM240F100I5)

137 MHz 47 94
Cyclone III

 

(EP3C5E144I7)

322 MHz 47 93
Cyclone IV

 

(EP4CE22F17C6)

400 MHz 47 91
Stratix III

 

(EP3SE110F780I3)

498 MHz 47 55 36

XILINX

FPGA Type Maximum ‘clk‘ Frequency Flip-Flops 4-LUTs Slices Macrocells
CoolRunnerII

 

(XC2C128-6-TQ144)

87 MHz 47 52
Spartan3

 

(XC3S50-5PQ208)

212 MHz 45 105 62
Spartan6

 

(XC6SLX9-3TQG144)

335 MHz 49 35
Virtex4

 

(XC4VLX15-12SF363)

449 MHz 47 103 61
Zync

 

(XC7Z010-3CLG400)

426 MHz 45 41

Key Features

  • Design Assurance Level A according to RTCA DO-254/ED-80 (April, 2000)
  • Fully compliant to the I2C-bus specification and user manual Rev. 5 – 9 October 2012 for Standard-mode, Fast-mode and Fast-mode Plus (Fm+)
  • Configurable data rate (100kHz, 400kHz or 1000kHz)
  • Support for all Options (Multi-master, Synchronization, Arbitration, Clock stretching, 10-bit slave address, General Call address, Software Reset and START byte)
  • Single clock domain fully synchronous design
  • Simple interface to user’s logic
  • TMR coded for SEU immunity (optional)
  • Technology independent (can be synthesized to any FPGA/CPLD vendor)

Block Diagram

I2C Master DO-254 IP Core Block Diagram

Technical Specifications

Foundry, Node
All
Maturity
Hardware Tested
Availability
Immediate
×
Semiconductor IP