SDRAM Controller DO-254 IP Core

The SDRAM Controller implements a controller for Single Data Rate Synchronous Dynamic Random Access Memory (SDR SDRAM) devices as specified in the JEDEC Standard No. 21-C Page 3.11.5.1 Release 12.

Single Data Rate SDRAM can accept one command and transfer one word of data per clock cycle. Typical clock frequencies are 100 and 133 MHz. Chips are made with a variety of data bus sizes. SDRAM is still being manufactured and the maturity of this technology makes it ideal for systems that need performance at a low cost.

The SDRAM Controller has been developed to DAL A according to the DO-254 / ED-80 and is accompanied by a Certification Kit. For lower DAL levels reduced documentation sets are available. The core is also available as a netlist for DAL D or projects not needing the full RTL source.

Implementation Details

Unless otherwise specified (marked with an *) all the runs have been performed with the default options of the respective tool .

The following example implementations are compatible with two MT48LC4M16A2 memory chips in parallel (each SDRAM chips contains 64Mb with 4K rows, 4 banks, 256 columns and 16bits per word).

The results are provided for an SDRAM Controller with the following configuration generics (see Table 1):

The following constraints were added:

• Clock period – 10 ns or 6 ns (100 MHz or 133 MHz)
• Input Data Setup – 1.5 ns
• Input Data Hold – 0 ns
• Clock to Output – 0 to 4.5 ns

In the tables below two results are shown for each device, the 1^st one is with ‘g_USE_ADVANCED_BST’ set to TRUE and the second set to FALSE.

ALTERA

XILINX