The SPI Slave IP Core implements an SPI Slave fully compliant to the SPI Standard (Motorola’s M68H11 Reference Manual).
The Serial Peripheral Interface (SPI) bus is a synchronous serial communication interface specification used for short distance communication, primarily in embedded systems. The interface was developed by Motorola and has become a de facto standard. Typical applications include Secure Digital cards and liquid crystal displays. SPI devices communicate in full duplex mode using a master-slave architecture with a single master. The master device originates the frame for reading and writing. Multiple slave devices are supported through selection with individual slave select (SS) lines.
The SPI Master IP Core has been developed to DAL A according to the DO-254 / ED-80 and is accompanied by a Certification Kit. For lower DAL levels reduced documentation sets are available. The core is also available as a netlist for DAL D or projects not needing the full RTL source.
Safe Core Devices provides two separate IP Cores, one for the SPI Slave IP Core and one for the SPI Master IP Core. If the system needs to be capable of transmitting and receiving both cores can be instantiated in the target device.
Implementation Details
Unless otherwise specified all the runs have been performed with the default options of the respective tool. Register placement on the IO has been disabled.
No constraints were added, so the results listed under the column “Maximum frequency of operation” are the worst case scenario (no multicycle, false paths, etc. defined).
The results are provided for an 8-bit word SPI Slave Core without TMR (Triple Module Redundancy), if TMR is used the number of registers will be triplicated, the combinatorial logic will also increase and there might be a penalty on the maximum ‘clk‘ frequency.
ACTEL / MICROSEMI
| FPGA Type | Maximum ‘clk‘ Frequency | Logic Modules (CORE) |
|---|---|---|
| ProASIC3
(A3P015 68QFN I Std) |
145 MHz | 85 |
| IGLOO
(AGL030V5 100VQPF I Std) |
130 MHz | 85 |
| Fusion
(AFS090 180QFN I Std) |
143 MHz | 85 |
| Axcelerator
(RTAX250S 208CQFP Mil Std) |
141 MHz | SEQUENTIAL (R-cells): 29
COMB (C-cells): 34 |
ALTERA
| FPGA Type | Maximum ‘clk’ Frequency | Flip-Flops | ALUTs | ALMs | Logic Cells |
|---|---|---|---|---|---|
| MAX II
(EPM240F100I5) |
147 MHz | 27 | – | – | 39 |
| Cyclone III
(EP3C5E144I7) |
350 MHz | 27 | – | – | 45 |
| Stratix II
(EP2S60F484I4) |
440 MHz | 27 | 26 | 20 | – |
| Stratix III
(EP3SE110F780I3) |
> 630 MHz | 27 | 25 | 17 | – |
| Stratix IV
(EP4SGX70HF35C2) |
> 700 MHz | 27 | 25 | 17 | – |
XILINX
| FPGA Type | Maximum ‘clk‘ Frequency | Flip-Flops | 4-LUTs | Slices | Macrocells |
|---|---|---|---|---|---|
| CoolRunnerII
(XC2C128-6-TQ144) |
67 MHz | 27 | – | – | 30 |
| Spartan3
(XC3S50-4PQ208 |
207 MHz | 30 | 57 | 38 | – |
| Virtex2
(XC2V40-4FG256) |
254 MHz | 27 | 66 | 40 | – |
| Virtex4
(XC4VLX15-12SF363) |
> 440 MHz | 30 | 65 | 41 | – |
| Virtex5
(XC5VLX30-3FF324) |
> 620 MHz | 27 | – | 15 | – |
