ARINC 429 Transmitter DO-254 IP Core

Overview

The ARINC 429 Tx IP Core implements a transmitter as specified in the ARINC Specification 429 Part 1-17.

This “Mark 33 Digital Information Transfer System (DITS)” specification defines how to transfer digital data between avionics systems elements. The transmission is done over a twisted and shielded pair of wires and bi-directional data flow is not permitted. An extra twisted and shielded pair of wires is used when data is required to flow both ways.

The ARINC 429 Rx Core has been developed to DAL A according to the DO-254 / ED-80 and is accompanied by a Certification Kit.

A radiation-hardened version with Triple Modular Redundancy (TMR) is also available.

Safe Core Devices provides two separate IP Cores, one for the ARINC 429 Rx IP Core and one for the ARINC 429 Tx IP Core. If the system needs to be capable of transmitting and receiving both cores can be instantiated in the target device.The ARINC 429 Tx IP Core is already being used in one program: a civil large airplane program, as DAL A.

Implementation Details

The following tables show some examples of implementing the A429 Tx Core in different technologies and devices. Note that the A429 Tx Core is technology independent, and therefore it can be implemented in any technology/device as long as it contains enough resources (Flip-Flops, gates, pins, etc.).

Unless otherwise specified all the runs have been performed with the default options of the respective tool. Register placement on the IO has been disabled.

No constraints were added, so the results listed under the column “Maximum ‘clk’ Frequency” are the worst case scenario (no multi-cycle, false paths, etc. defined).

The results are provided for an A429 Tx Core without TMR (Triple Module Redundancy), if TMR is used the number of registers will be triplicated, the combinatorial logic will also increase and there might be a penalty on the maximum ‘clk’ frequency.

ACTEL / MICROSEMI

FPGA Type Maximum ‘clk‘ Frequency Logic Modules (CORE)
ProASIC3

 

(A3P015 68QFN I Std)

147 MHz 133
IGLOO

 

(AGL030V5 100VQFP I Std)

138 MHz 136
Fusion

 

(AFS090 180QFN I Std)

143 MHz 133
Axcelerator

 

(RTAX250S 208CQFP Mil Std)

199 MHz SEQUENTIAL (R-cells): 43

 

COMB (C-cells): 79

ALTERA

FPGA Type Maximum ‘clk’ Frequency Flip-Flops ALUTs ALMs Logic Cells
MAX II

 

(EPM240F100I5)

142 MHz 43 69
Cyclone III

 

(EP3C5E144I7)

> 350 MHz 43 71
Stratix II

 

(EP2S60F484I4)

> 400 MHz 43 29 34
Stratix III

 

(EP3SE110F780I3)

> 525 MHz 43 28 34
Stratix IV

 

(EP4SGX70HF35C2)

> 650 MHz 43 26 32

XILINX

FPGA Type Maximum ‘clk‘ Frequency Flip-Flops 4-LUTs Slices Macrocells
CoolRunnerII

 

(XC2C128-6-TQ144)

126 MHz 43 58
Spartan3

 

(XC3S50-4PQ208)

197 MHz 43 112 61
Virtex2

 

(XC2V40-4FG256)

230 MHz 43 113 62
Virtex4

 

(XC4VLX15-12SF363)

> 430 MHz 43 116 62
Virtex5

 

(XC5VLX30-3FF324)

> 520 MHz 43 24

Key Features

  • Compliant to ARINC Specification 429-17 (May 17, 2004)
  • Design Assurance Level A according to DO-254 / ED-80
  • Single clock domain fully synchronous design
  • Configurable data rate
  • Multiple error checking (frequency, gap, parity and form)
  • Interfaces to standard line drivers without additional logic
  • Simple interface to user’s logic
  • TMR coding for radiation-hardening (optional)
  • Technology independent, can be synthesized to any FPGA / ASIC vendor.

Block Diagram

ARINC 429 Transmitter DO-254 IP Core Block Diagram

Technical Specifications

Foundry, Node
All
Maturity
Integrated and Flying in aircraft.
Availability
Immediate
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Semiconductor IP