CAN FD Controller DO-254 IP Core

Overview

The CAN FD Controller implements a Controller Area Network as specified in the ISO 11898:2015 Part 1, supporting both Classical and Flexible Data Rate CAN frame formats. The CAN FD Controller supports bit rates up to 1 Mbit/s for Classical CAN frame format and up to 10Mbit/s for Flexible Data Rate format.

The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed real-time control with a very high level of security. The new Flexible Data Rate frame format introduced in ISO 11898:2015 Part 1 allows higher data rates and larger payloads per frame.

Its domain of application range from high speed networks to low cost multiplex wiring. In airborne and automotive industries, electronic control units, sensors, and actuators are connected using CAN.

The CAN FD Controller has been developed to DAL A according to the DO-254 / ED-80 and is accompanied by a Certification Kit. For lower DAL levels reduced documentation sets are available. The core is also available as encrypted source code for DAL D projects or projects not requiring DO-254 compliance.

Implementation Details

The following tables show some examples of implementing the CAN FD Controller in different technologies and devices. Note that the CAN FD Controller is technology independent, and therefore it can be implemented in any technology/device as long as it contains enough resources (Flip-Flops, gates, pins, etc.).

Unless otherwise specified all the runs have been performed with the default options of the respective tool. Register placement on the IO has been disabled.

No constraints were added, so the results listed under the column “Maximum ‘clk’ Frequency” are the worst case scenario (no multicycle, false paths, etc. defined).

The results are provided for a CAN FD Core  is without TMR (Triple Module Redundancy). If TMR is used the number of registers will be triplicated, the combinatorial logic will also increase and there might be a penalty on the Maximum ‘clk’ Frequency.

MICROSEMI

FPGA Type Maximum ‘clk’

 

Frequency

LUTs used FFs used Interface 

 

LUTs used

Interface

 

FFs used

IGLOO2

 

(M2GL025T)

116 Mhz 7587 3026 36 36
PolarFire

 

(MPF100T)

144 Mhz 7557 3027 12 12

XILINX

FPGA Type Maximum ‘clk’

 

Frequency

LUTs used FFs used
Spartan 7

 

(XC7S100FGGA676-1)

98 Mhz 5000 3067
Zync UltraScale+

 

(XCZU2EG-SFVA625-1)

157 Mhz 4901 3066

Key Features

  • Design Assurance Level A according to RTCA DO-254/ED-80 (April, 2000)
  • Fully compliant to ISO 11898-1:2015
  • Supports both Classical and Flexible Data Rate frame formats
  • Tested as specified in the ISO 16845-1:2016
  • Single clock domain fully synchronous design
  • Configurable data rate up to 1 Mbit/s for Classical frames and up to 10 Mbit/s for Flexible Data Rate frames
  • Interfaces to standard transceivers without additional logic
  • Simple interface to user’s logic
  • TMR coded for SEU immunity (optional)
  • Technology independent (can be synthesized to any FPGA/CPLD vendor)

Block Diagram

CAN FD Controller DO-254 IP Core Block Diagram

Technical Specifications

Foundry, Node
All
Maturity
Hardware Tested
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Semiconductor IP