The Universal Asynchronous Receiver/Transmitter (UART) is a hardware device that translates data between parallel and serial forms. UARTs are commonly used in conjunction with communication standards such as TIA (formerly EIA) RS-232, RS-422 or RS-485. The universal designation indicates that the data format and transmission speeds are configurable. The electric signaling levels and methods (such as differential signaling etc.) are handled by a driver circuit external to the UART.
The UART IP Core has been developed to DAL A according to the DO-254. For lower DAL levels reduced documentation sets are available. The core is also available as a netlist for DAL D or projects not needing the full RTL source.
DO-254 UART
Overview
Key Features
- Design Assurance Level A according to RTCA DO-254/ED-80 (April, 2000)
- Configurable baud rate, number of data bits, parity and stop bits.
- Fully deterministic handshake interface that allows easy handling of reception/transmission requests
- Single clock domain fully synchronous design
- Interface to standard RS-232 drivers, so it can be used without modification in standard hardware
- Simple interface to user’s logic
- TMR coded for SEU immunity (optional)
- Technology independent (can be synthesized to any FPGA/CPLD vendor)
Block Diagram
Technical Specifications
Foundry, Node
All
Maturity
Integrated and Flying in aircraft.
Availability
Immediate