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AMBA AHB / APB IP

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Compare 178 AMBA AHB / APB IP from 26 vendors (1 - 10)
  • Tessent Bus Monitor
    • Full transaction and trace-level visibility of on-chip bus traffic
    • Wide range of measurements, analytics statistics: Transactions, Bus cycles, latency, duration, beats, bus concurrency
    • Supports AXI, ACE, ACE-lite
    • Run-time configurable
    Block Diagram -- Tessent Bus Monitor
  • I3C Lite Advanced Target
    • Advanced I3C features
    • Hot join
    • In-band interrupts
    • Timing Control
    Block Diagram -- I3C Lite Advanced Target
  • GDDR6 Memory Controller IP
    • JEDEC GDDR6 standard JESD250B
    • Fast frequency switching
    • Flexible Configuration
    Block Diagram -- GDDR6 Memory Controller IP
  • SD 4.0 UHS-II PHY TSMC 28nm HPM North-South
    • Compliant with SD Specifications Part 1 UHS-II Addendum v1
    • Supports data rate between 390 Mbps to 1.56 Gbps per lane
    • Supports peak interface speed of 3.12 Gbps in Half-duplex mode; 1.56 Gbps in Full-duplex mode
    • Sub-LVDS differential PHY signaling
    Block Diagram -- SD 4.0 UHS-II PHY TSMC 28nm HPM North-South
  • RISC-V Compliant Platform Level Interrupt Controller
    • AHB-Lite Interface with programmable address and data width
    • User defined number of Interrupt Sources & Targets
    Block Diagram -- RISC-V Compliant Platform Level Interrupt Controller
  • AHB-Lite Timer
    • AHB-Lite Interface with programmable address and data width
    • User defined number of counters (Up to 32)
    • Programmable time base derived from AHB-Lite bus clock
    Block Diagram -- AHB-Lite Timer
  • APB4 General Purpose Input/Output Module
    • Compliant with AMBA APB v2.0 Specification
    • User-defined number of Bi-directional General Purpose IO
    • Automatic synchronisation of General Inputs to Bus Clock
    • Each General Output configurable as push-pull or open-drain
    Block Diagram -- APB4 General Purpose Input/Output Module
  • AHB-Lite General Purpose Memory Module
    • Full support for AMBA 3 AHB-Lite protocol
    • Fully parameterized
    • User-defined address and byte-aligned data widths supported
    • Configurable memory depth, limited only by target technology capability
    Block Diagram -- AHB-Lite General Purpose Memory Module
  • APB4 Multiplexer
    • Full support for APB version 2.0 (APB4) protocol
    • Fully parameterized IP with:
    • Support for user defined address mapping per peripheral
    Block Diagram -- APB4 Multiplexer
  • AHB-Lite Multilayer Switch
    • AMBA AHB-Lite Compatible
    • Fully parameterized
    • Unlimited number of Bus Masters and Slaves
    • Slave side arbitration
    Block Diagram -- AHB-Lite Multilayer Switch
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Semiconductor IP