Cadence provides a mature and comprehensive Verification IP (VIP) for the Coherent Hub Interface (CHI) specification, which is part of the Arm® AMBA® family of protocols. Incorporating the latest protocol updates, the Cadence® Verification IP for AXI provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for CHI provides a highly capable compliance verification solution that supports simulation, formal analysis, and hardware acceleration platforms. Cadence provides an integrated solution for interconnect verification, which supports the verification of coherent interconnect and performance analysis that provides automated generation of testbenches. The VIP runs on all major simulators and supports SystemVerilog and e verification languages, along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).
Supported specification: AMBA 5 CHI A, B, C, D, E, and F.
