AMBA AHB Direct Memory Acess (DMA) Controller

Key Features

  • Multiple independent DMA channels with direct AHB bus interface.
  • DMA transfers between AHB memory devices and I/O ports.
  • Scatter-gather allows DMA to merge multiple data source to contiguous space.
  • Supports both hardware initiated transfer and software initiated transfer.
  • Supports burst transfer to maximize data bandwidth.
  • Automatic address increment or decrement.
  • Interrupt generation on transfer completion.
  • Burst data access on the AHB interface and user I/O interface.
  • Handles wait state insertion by any slave devices.
  • Supports all slave device responses: OKAY, RETRY, SPLIT and ERROR.
  • Master does not insert wait state on AHB bus thus maximize data bandwidth.
  • No delay insertion on data transfer between user I/O interface and AHB bus.
  • Separate user interface for DMA control register programming.
  • User interface matches seamlessly with other Eureka Technology IP cores.
  • Optimized for ASIC and PLD implementations.

Block Diagram

AMBA AHB Direct Memory Acess (DMA) Controller Block Diagram

Technical Specifications

Short description
AMBA AHB Direct Memory Acess (DMA) Controller
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Semiconductor IP