AMBA AHB Bus Master

Key Features

Supports AHB bus interface to the ARM CPU.
User interface designed for high speed access to any slave devices on the AHB Bus.
User specified single or burst data access on the AHB interface and user interface.
Handles wait state insertion by any slave devices.
Automatic bus arbitration.
Supports all slave device responses: OKAY, RETRY, SPLIT and ERROR.
No delay insertion on data transfer between user interface and AHB bus.
Supports bus parking.
Efficient user interface optimized for on-chip data communication.
User interface matches seamlessly with Eureka Technology DMA controller or PCI bridge.
Optimized for ASIC and PLD implementations, including Excalibur PLD.

Availability

now