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Compare 229 IP for TSMC from 14 vendors (1 - 10)
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  • 3nm
  • TSMC CLN3FFP HBM4 PHY
    • IGAHBMZ03A is a High Bandwidth Memory 4 Physical  Layer (HBM4 PHY) that is compliant with JEDEC HBM4 DRAM Specification JESD270-4.
    • Fabricated in the TSMC 3 nm Advanced process node (N3P), it supports the data rate up to 12 Gbps per data pin in the DDR PHY Interface (DFI)-like 1:4 clock frequency ratio (HBM4 controller clock: WDQS = 1:4).
    Block Diagram -- TSMC CLN3FFP HBM4 PHY
  • Crystal Oscillators
    • The crystal oscillator macros are available in a wide range of industry-standard quartz crystals and MEMS resonators operating in the fundamental mode in the 32 kHz to 80 MHz range.
    • These oscillators, which are both power and area efficient, have a programmable transconductance to allow users to find the optimal balance between jitter and power consumption.
    Block Diagram -- Crystal Oscillators
  • LDO Voltage Regulator, Adjustable 0.45 V to 0.9 V Output, 30 mA, TSMC N3P
    • The LDO IP is a 1.2V low-quiescent-current adjustable output voltage Low-Drop-Out (LDO) Linear Regulator implemented in the TSMC 3nm N3P CMOS process technology.
    • Its low sleep current, 30 mA maximum current, output voltage adjustability and precision make it especially suitable for use as an integrated voltage regulation source for subsystems implemented in analog, digital, mixed-signal and RF ASICs and SoCs.
    Block Diagram -- LDO Voltage Regulator, Adjustable 0.45 V to 0.9 V Output, 30 mA,  TSMC N3P
  • LDO Voltage Regulator, 250 mA, TSMC N3P
    • TSMC 3nm FinFET process
    • Input voltage: 1.2 V
    • Output voltage range: 0.45 V to 0.9 V
    • Vout adjustable in 50 mV increments
    Block Diagram -- LDO Voltage Regulator, 250 mA, TSMC N3P
  • Core Powered Wide Range Programmable Integer PLL on TSMC CLN3P-CLN3X
    • Entirely core voltage powered, needs no analog supply voltage
    • Electrically Programmable PLL for multiple applications
    • Wide Ranges of Input and Output Frequency for diverse clocking needs
    • Implemented with Analog Bits’ proprietary architecture
    Block Diagram -- Core Powered Wide Range Programmable Integer PLL on TSMC CLN3P-CLN3X
  • Core Powered Wide Range Programmable Integer PLL on TSMC CLN3E
    • Entirely core voltage powered, needs no analog supply voltage
    • Electrically Programmable PLL for multiple applications
    • Wide Ranges of Input and Output Frequency for diverse clocking needs
    • Implemented with Analog Bits’ proprietary architecture
    Block Diagram -- Core Powered Wide Range Programmable Integer PLL on TSMC CLN3E
  • 18-40MHz Crystal Oscillator on TSMC CLN3P-CLN3X
    • Crystal Oscillator pad macro that supports industry standard crystals
    • Uses standard CMOS transistors
    • Crystal Oscillation Mode: Fundamental
    • Power down option for IDDQ testing
    Block Diagram -- 18-40MHz Crystal Oscillator on TSMC CLN3P-CLN3X
  • TSMC N3P 1.8V IO Platform supporting cells
    • Compliant with eMMC 5.1 HS400, SD 6.0 SDR104, DDR50, JESD8-7a (1.2V/1.8V) and JESD8c.01 (3.3V)
    • Fully integrated hard macro with high speed IOs and DLL/delay lines
    • Fine resolution DLL/delay lines for HS400 strobe and HS200/SDR104 auto-tuning
    • Easy to integrate with the highly optimized Synopsys SD/eMMC Host Controller IP, providing a complete low risk solution
    Block Diagram -- TSMC N3P 1.8V IO Platform supporting cells
  • Temperature Sensor (Digital Output)
    • Measurement Range: -20°C to +100°C
    • Uncalibrated Accuracy: ±6°C
    Block Diagram -- Temperature Sensor (Digital Output)
  • Sleep Management Subsystem
    • Power-On-Reset
    • Programmable relaxation oscillator
    • Low Power Comparator
    Block Diagram -- Sleep Management Subsystem
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