IP for TSMC

Fractional-N Phase locked loop frequency synthesizer is intended for ASIC clock generation.
The Fractional-N PLL loop with 2GHz-4GHz VCO has high phase noise performance and ultra-fine frequency tuning step.
VCO Sub-band auto select (SAS) system allows to find automatically appropriate sub-band for VCO on locked PLL.

Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions
Synopsys SD/eMMC PHY is a hard IP that can be used to implement a single interface that can accomplish 4-bit, 8-bit eMMC & 4-bit SD operations
It includes an optional digi logic circuitry which is required for high-speed operations
It complies with eMMC 5.1 (JESD84-B51A) and SDIO 6.0 JEDEC standards

Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions
Synopsys SD/eMMC PHY is a hard IP that can be used to implement a single interface that can accomplish 4-bit, 8-bit eMMC & 4-bit SD operations
It includes an optional digi logic circuitry which is required for high-speed operations
It complies with eMMC 5.1 (JESD84-B51A) and SDIO 6.0 JEDEC standards

The AI and HPC industries are advancing toward chiplet-based designs to achieve superior performance, as traditional monolithic SoCs face scaling challenges
Heterogeneous integration is driving semiconductor innovation but adds complexity to chip design, requiring advanced testing methodologies and improved Automated Test Equipment (ATE)
Increasing test patterns and limited package pins demand high-bandwidth IOs, while advancements in ATE capabilities further necessitate optimized GPIOs to support higher-speed, efficient and low-cost testing
Synopsys High-Speed Test IO IP is a cutting-edge IO interface solution that enables efficient, high-speed testing of complex semiconductor designs while minimizing hardware complexity and cost