IP for TSMC

Compare 232 IP for TSMC from 14 vendors (1 - 10)

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PCIe 6.0 PHY, TSMC N3A x4 1.2V, North/South (vertical) poly orientation for Automotive, ASIL B Random, AEC-Q100 Grade 2
- Supports the latest features of PCIe 6.x and CXL 3.x specifications
- Supports PAM-4 signaling and up to x16 lane configurations with bifurcation
- Delivers more power efficiency across channels with unique DSP algorithms
- Enables near zero link downtime with patent-pending diagnostic features
USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
- Supports 40 Gbps, 20 Gbps, 10 Gbps, and 5 Gbps data rates
- Supports 480 Mbps, 12 Mbps, and 1.5 Mbps data rates
- x1 and x2 configurations (USB 3.2 and USB 3.1 PHY only)
- Low active and standby power
- Small area for low silicon cost
USB4 PHY - TSMC N3E 1.2V, North/South Poly Orientation
- Supports 40 Gbps, 20 Gbps, 10 Gbps, and 5 Gbps data rates
- Supports 480 Mbps, 12 Mbps, and 1.5 Mbps data rates
- x1 and x2 configurations (USB 3.2 and USB 3.1 PHY only)
- Low active and standby power
- Small area for low silicon cost
USB4 PHY - TSMC N5 1.2V, North/South Poly Orientation
- Supports 40 Gbps, 20 Gbps, 10 Gbps, and 5 Gbps data rates
- Supports 480 Mbps, 12 Mbps, and 1.5 Mbps data rates
- x1 and x2 configurations (USB 3.2 and USB 3.1 PHY only)
- Low active and standby power
USB4 PHY - TSMC N3P 1.2V, North/South Poly Orientation
- Supports 40 Gbps, 20 Gbps, 10 Gbps, and 5 Gbps data rates
- Supports 480 Mbps, 12 Mbps, and 1.5 Mbps data rates
- x1 and x2 configurations (USB 3.2 and USB 3.1 PHY only)
- Low active and standby power
- Small area for low silicon cost
TSMC CLN3FFP HBM4 PHY
- IGAHBMZ03A is a High Bandwidth Memory 4 Physical Layer (HBM4 PHY) that is compliant with JEDEC HBM4 DRAM Specification JESD270-4.
- Fabricated in the TSMC 3 nm Advanced process node (N3P), it supports the data rate up to 12 Gbps per data pin in the DDR PHY Interface (DFI)-like 1:4 clock frequency ratio (HBM4 controller clock: WDQS = 1:4).
Crystal Oscillators
- The crystal oscillator macros are available in a wide range of industry-standard quartz crystals and MEMS resonators operating in the fundamental mode in the 32 kHz to 80 MHz range.
- These oscillators, which are both power and area efficient, have a programmable transconductance to allow users to find the optimal balance between jitter and power consumption.
Free running oscillators
- Compact and low power
- No external components
- Baseline CMOS logic process masks only
- Excellent frequency precision over PVT after trimming
LDO Voltage Regulator, Adjustable 0.45 V to 0.9 V Output, 30 mA, TSMC N3P
- The LDO IP is a 1.2V low-quiescent-current adjustable output voltage Low-Drop-Out (LDO) Linear Regulator implemented in the TSMC 3nm N3P CMOS process technology.
- Its low sleep current, 30 mA maximum current, output voltage adjustability and precision make it especially suitable for use as an integrated voltage regulation source for subsystems implemented in analog, digital, mixed-signal and RF ASICs and SoCs.
LDO Voltage Regulator, 250 mA, TSMC N3P
- TSMC 3nm FinFET process
- Input voltage: 1.2 V
- Output voltage range: 0.45 V to 0.9 V
- Vout adjustable in 50 mV increments