IP for TSMC

Compare 245 IP for TSMC from 15 vendors (1 - 10)

Filter:

LDO Voltage Regulator, Adjustable 0.45 V to 0.9 V Output, 30 mA, TSMC N3P
- The LDO IP is a 1.2V low-quiescent-current adjustable output voltage Low-Drop-Out (LDO) Linear Regulator implemented in the TSMC 3nm N3P CMOS process technology.
- Its low sleep current, 30 mA maximum current, output voltage adjustability and precision make it especially suitable for use as an integrated voltage regulation source for subsystems implemented in analog, digital, mixed-signal and RF ASICs and SoCs.
LDO Voltage Regulator, 250 mA, TSMC N3P
- TSMC 3nm FinFET process
- Input voltage: 1.2 V
- Output voltage range: 0.45 V to 0.9 V
- Vout adjustable in 50 mV increments
Core Powered Wide Range Programmable Integer PLL on TSMC CLN3P-CLN3X
- Entirely core voltage powered, needs no analog supply voltage
- Electrically Programmable PLL for multiple applications
- Wide Ranges of Input and Output Frequency for diverse clocking needs
- Implemented with Analog Bits’ proprietary architecture
Core Powered Wide Range Programmable Integer PLL on TSMC CLN3E
- Entirely core voltage powered, needs no analog supply voltage
- Electrically Programmable PLL for multiple applications
- Wide Ranges of Input and Output Frequency for diverse clocking needs
- Implemented with Analog Bits’ proprietary architecture
18-40MHz Crystal Oscillator on TSMC CLN3P-CLN3X
- Crystal Oscillator pad macro that supports industry standard crystals
- Uses standard CMOS transistors
- Crystal Oscillation Mode: Fundamental
- Power down option for IDDQ testing
TSMC N3P 1.8V IO Platform supporting cells
- Compliant with eMMC 5.1 HS400, SD 6.0 SDR104, DDR50, JESD8-7a (1.2V/1.8V) and JESD8c.01 (3.3V)
- Fully integrated hard macro with high speed IOs and DLL/delay lines
- Fine resolution DLL/delay lines for HS400 strobe and HS200/SDR104 auto-tuning
- Easy to integrate with the highly optimized Synopsys SD/eMMC Host Controller IP, providing a complete low risk solution
PVT SENSOR
- SGC21713_IP007708_GF_22FDX can be used in a control loop to minimize the voltage for a given frequency or maximize frequency for a given voltage
- Based on a group of sensors, it permits PVT and aging tracking, while allowing the identification of the actual variable that changed
- Designed to achieve 3% overall accuracy (over Load / Line / Temp), it is specified from TJ = –40°C to +125°C.
Temperature Sensor (Digital Output)
- Measurement Range: -20°C to +100°C
- Uncalibrated Accuracy: ±6°C
Sleep Management Subsystem
- Power-On-Reset
- Programmable relaxation oscillator
- Low Power Comparator
Power Management Subsystem
- The agilePMU Subsystem is an efficient and highly integrated Power Management Unit for SoCs/ASICs.
- Featuring a Power-On-Reset (POR), multiple Low Drop-Out (LDO) regulators, and an associated reference generator.
- The agilePMU Subsystem is designed to ensure low power consumption while providing optimal power management capabilities.