Memory Controller/PHY IP for TSMC
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20
Memory Controller/PHY IP
for TSMC
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- 3nm
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TSMC CLN3FFP HBM4 PHY
- IGAHBMZ03A is a High Bandwidth Memory 4 Physical Layer (HBM4 PHY) that is compliant with JEDEC HBM4 DRAM Specification JESD270-4.
- Fabricated in the TSMC 3 nm Advanced process node (N3P), it supports the data rate up to 12 Gbps per data pin in the DDR PHY Interface (DFI)-like 1:4 clock frequency ratio (HBM4 controller clock: WDQS = 1:4).
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TSMC N3P 1.8V IO Platform supporting cells
- Compliant with eMMC 5.1 HS400, SD 6.0 SDR104, DDR50, JESD8-7a (1.2V/1.8V) and JESD8c.01 (3.3V)
- Fully integrated hard macro with high speed IOs and DLL/delay lines
- Fine resolution DLL/delay lines for HS400 strobe and HS200/SDR104 auto-tuning
- Easy to integrate with the highly optimized Synopsys SD/eMMC Host Controller IP, providing a complete low risk solution
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HBM3 PHY V2 (Hard) - TSMC N3P
- Supports 2.5D-based JEDEC standard HBM3 DRAMs with data rates up to 9600 Mbps
- 16 independent 64-bit memory channels
- Pseudo-channel operation supported to enable up to 32 32-bit pseudo-channels with 1024-bit PHY
- Supports up to 4 trained frequencies with <5us switching time
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TSMC N3P SD/eMMC PHY North/South Poly Orientation
- Compliant with eMMC 5.1 HS400, SD 6.0 SDR104, DDR50, JESD8-7a (1.2V/1.8V) and JESD8c.01 (3.3V)
- Fully integrated hard macro with high speed IOs and DLL/delay lines
- Fine resolution DLL/delay lines for HS400 strobe and HS200/SDR104 auto-tuning
- Easy to integrate with the highly optimized Synopsys SD/eMMC Host Controller IP, providing a complete low risk solution
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TSMC N3E SD/eMMC PHY North/South Poly Orientation
- Compliant with eMMC 5.1 HS400, SD 6.0 SDR104, DDR50, JESD8-7a (1.2V/1.8V) and JESD8c.01 (3.3V)
- Fully integrated hard macro with high speed IOs and DLL/delay lines
- Fine resolution DLL/delay lines for HS400 strobe and HS200/SDR104 auto-tuning
- Easy to integrate with the highly optimized Synopsys SD/eMMC Host Controller IP, providing a complete low risk solution
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HBM3 PHY V2 - TSMC N3E
- Supports 2.5D-based JEDEC standard HBM3 DRAMs with data rates up to 9600 Mbps
- 16 independent 64-bit memory channels
- Pseudo-channel operation supported to enable up to 32 32-bit pseudo-channels with 1024-bit PHY
- Supports up to 4 trained frequencies with <5us switching time
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HBM3 V2 Solution enabling access to HBM3 Controller and HBM3 PHY in TSMC N3E
- JEDEC HBM 3.0 DRAM
- DFI 5.0 compliant interface to HBM3 PHY
- Multiport Arm® AMBA® interface (4 AXI AXI™) with managed QoS or single-port host interface, per pseudo-channel
- Data rates up to 6.4 Gbps (DFI 1:1:2) (1.6GHz controller clock)
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LPDDR5X/5/4X PHY - TSMC N3P
- Supports JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs
- Support for data rates up to 8533 Mbps
- Designed for rapid integration with Synopsys LPDDR5X/5/4X controller for a complete DDR interface solution
- DFI 5.0 controller interface
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LPDDR5X/5/4X PHY - TSMC N3E
- Supports JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs
- Support for data rates up to 8533 Mbps
- Designed for rapid integration with Synopsys LPDDR5X/5/4X controller for a complete DDR interface solution
- DFI 5.0 controller interface
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LPDDR5X/5/4X PHY - TSMC N3A for Automotive, ASIL B Random, AEC-Q100 Grade 2
- Supports JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs
- Support for data rates up to 8533 Mbps
- Designed for rapid integration with Synopsys LPDDR5X/5/4X controller for a complete DDR interface solution
- DFI 5.0 controller interface
