Memory Controller/PHY IP for TSMC

The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performance LPDDR6, LPDDR5X, and/or LPDDR5 SDRAM interfaces operating at up to 14.4 Gbps
With flexible configuration options, the LPDDR6/5X/5 PHY IP can be used in a variety of applications supporting LPDDR6, LPDDR5X, and/or LPDDR5 SDRAMs, precisely targeting the specific power, performance, and area (PPA) requirements of these systems
LPDDR6 SDRAM’s combination of high bandwidth, capacity, low power, and cost effectiveness makes LPDDR6/5X/5 SDRAMs an attractive solution for traditional and new markets
The LPDDR6/5X/5 PHY IP is designed to appeal to a variety of applications including: * Traditional mobile environments * Consumer products * Automotive solutions * Artificial intelligence * Data center applications

The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performance LPDDR6, LPDDR5X, and/or LPDDR5 SDRAM interfaces operating at up to 14.4 Gbps
With flexible configuration options, the LPDDR6/5X/5 PHY IP can be used in a variety of applications supporting LPDDR6, LPDDR5X, and/or LPDDR5 SDRAMs, precisely targeting the specific power, performance, and area (PPA) requirements of these systems
LPDDR6 SDRAM’s combination of high bandwidth, capacity, low power, and cost effectiveness makes LPDDR6/5X/5 SDRAMs an attractive solution for traditional and new markets
The LPDDR6/5X/5 PHY IP is designed to appeal to a variety of applications including: * Traditional mobile environments * Consumer products * Automotive solutions * Artificial intelligence * Data center applications

The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performance LPDDR6, LPDDR5X, and/or LPDDR5 SDRAM interfaces operating at up to 14.4 Gbps
With flexible configuration options, the LPDDR6/5X/5 PHY IP can be used in a variety of applications supporting LPDDR6, LPDDR5X, and/or LPDDR5 SDRAMs, precisely targeting the specific power, performance, and area (PPA) requirements of these systems
LPDDR6 SDRAM’s combination of high bandwidth, capacity, low power, and cost effectiveness makes LPDDR6/5X/5 SDRAMs an attractive solution for traditional and new markets
The LPDDR6/5X/5 PHY IP is designed to appeal to a variety of applications including: * Traditional mobile environments * Consumer products * Automotive solutions * Artificial intelligence * Data center applications

Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions
Synopsys SD/eMMC PHY is a hard IP that can be used to implement a single interface that can accomplish 4-bit, 8-bit eMMC & 4-bit SD operations
It includes an optional digi logic circuitry which is required for high-speed operations
It complies with eMMC 5.1 (JESD84-B51A) and SDIO 6.0 JEDEC standards

Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions
Synopsys SD/eMMC PHY is a hard IP that can be used to implement a single interface that can accomplish 4-bit, 8-bit eMMC & 4-bit SD operations
It includes an optional digi logic circuitry which is required for high-speed operations
It complies with eMMC 5.1 (JESD84-B51A) and SDIO 6.0 JEDEC standards

IGAHBMZ03A is a High Bandwidth Memory 4 Physical Layer (HBM4 PHY) that is compliant with JEDEC HBM4 DRAM Specification JESD270-4.
Fabricated in the TSMC 3 nm Advanced process node (N3P), it supports the data rate up to 12 Gbps per data pin in the DDR PHY Interface (DFI)-like 1:4 clock frequency ratio (HBM4 controller clock: WDQS = 1:4).

Supports 2.5D-based JEDEC standard HBM3 DRAMs with data rates up to 9600 Mbps
16 independent 64-bit memory channels
Pseudo-channel operation supported to enable up to 32 32-bit pseudo-channels with 1024-bit PHY
Supports up to 4 trained frequencies with <5us switching time

Supports 2.5D-based JEDEC standard HBM3 DRAMs with data rates up to 9600 Mbps
16 independent 64-bit memory channels
Pseudo-channel operation supported to enable up to 32 32-bit pseudo-channels with 1024-bit PHY
Supports up to 4 trained frequencies with <5us switching time

JEDEC HBM 3.0 DRAM
DFI 5.0 compliant interface to HBM3 PHY
Multiport Arm® AMBA® interface (4 AXI AXI™) with managed QoS or single-port host interface, per pseudo-channel
Data rates up to 6.4 Gbps (DFI 1:1:2) (1.6GHz controller clock)

Supports JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs
Support for data rates up to 8533 Mbps
Designed for rapid integration with Synopsys LPDDR5X/5/4X controller for a complete DDR interface solution
DFI 5.0 controller interface