Memory & Libraries IP for TSMC

Compare 31 Memory & Libraries IP for TSMC from 4 vendors (1 - 10)

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Standard Cell Library, Low Voltage Operation 0.45 V TSMC N3P
- Nominal voltage of 0.75 V +/-10 %
- Low voltage of 0.45 V +/-10 %
- Track height: 7.5T
- Operating temperature: -40°C to 125°C
Differential Output Driver on TSMC CLN3P-CLN3X
- Wide output frequency range support for diverse clocking needs
- Implemented with Analog Bits’ proprietary architecture
- Low power consumption
- Requires no additional on-chip components or band-gaps, minimizing power consumption
Differential Output Driver on TSMC CLN3E
- Wide output frequency range support for diverse clocking needs
- Implemented with Analog Bits’ proprietary architecture
- Low power consumption
- Requires no additional on-chip components or band-gaps, minimizing power consumption
CML Buffer on TSMC CLN3P-CLN3X
- CML differential buffer for on-chip applications
- Wide Ranges of input frequencies for diverse clocking and data needs
- Implemented with Analog Bits’ proprietary architecture
- Requires no additional on-chip components or band-gaps, minimizing power consumption
CML Buffer on TSMC CLN3E
- CML differential buffer for on-chip applications
- Wide Ranges of input frequencies for diverse clocking and data needs
- Implemented with Analog Bits’ proprietary architecture
- Requires no additional on-chip components or band-gaps, minimizing power consumption
TSMC 3nm (N3E) 1.2V/1.8V GPIO Libraries
- Supports 1.8V/2.5V/3.3V mixed-voltage-tolerant/failsafe output buffer
- Fully programmable output driver strengths, input Schmitt trigger, and output slew rate
- Supports circuit-under-pad (CUP), non-CUP-inline and staggered-bond pad placement
- Supports retention and bus-keeper feature
TSMC 3nm (N3E) 1.2V/1.8V GPIO with 1.8V Failsafe Libraries
- Supports 1.8V/2.5V/3.3V mixed-voltage-tolerant/failsafe output buffer
- Fully programmable output driver strengths, input Schmitt trigger, and output slew rate
- Supports circuit-under-pad (CUP), non-CUP-inline and staggered-bond pad placement
- Supports retention and bus-keeper feature
TSMC 3nm (N3E) 1.2V/1.8V GPIO with 1.8V Failsafe Libraries, multiple metalstacks
- Supports 1.8V/2.5V/3.3V mixed-voltage-tolerant/failsafe output buffer
- Fully programmable output driver strengths, input Schmitt trigger, and output slew rate
- Supports circuit-under-pad (CUP), non-CUP-inline and staggered-bond pad placement
- Supports retention and bus-keeper feature
TSMC 3nm (N3E) 1.8V SD/eMMC IO
- Completely hardened PHY solution along with programmable delay chains & I/Os
- Fully selectable output impedance
- Compliant with eMMC 5.1 (JESD84-B51A) and SDIO 3.0 JEDEC Standard
- Automotive G1/G2 supported, ASIL-B certified
TSMC 3nm (N3E) 1.2V LVDS Tx/Rx with 1.8V BGR
- Maximum operating speed: up to 3.4GBPS
- Compatibility with TIA/EIA - 644-A for greater interoperability
- Loop back option supported for both Pre/Post driver in LVDS TX
- HBM 2KV, CDM 500V (up to 7A)