Fractional-N Phase locked loop frequency synthesizer is intended for ASIC clock generation. The Fractional-N PLL loop with 2GHz-4GHz VCO has high phase noise performance and ultra-fine frequency tuning step.
VCO Sub-band auto select (SAS) system allows to find automatically appropriate sub-band for VCO on locked PLL.
The block embeds reference current sources.
Silicon area: 0.01254mm2 (108um x 115um)
ELECTRICAL CHARACTERISTICS
|
Parameter |
Symbol |
Conditions |
Value |
Units |
||
|
min |
typ |
max |
||||
|
Supply voltage |
PLL_VDD |
- |
0.675 |
0.75 |
0.825 |
V |
|
Operating temperature range |
Tj |
Junction |
-40 |
27 |
125 |
ºС |
|
Output frequency |
Fout |
- |
25 |
- |
4000 |
MHz |
|
Phase noise |
LOPN |
at 10MHz |
- |
-107 |
- |
dBc/Hz |
|
at 1GHz |
- |
-147 |
- |
dBc/Hz |
||
|
Output clock period jitter |
Jperiod |
- |
- |
0.6 |
- |
ps |
|
Reference frequency |
Fref |
- |
4.0 |
- |
1600 |
MHz |
|
Lock time |
Tlock |
- |
- |
50 |
- |
us |
|
Start-up time |
Tstart |
- |
- |
3.1 |
- |
ms |
|
Output frequency fine tuning range |
A |
From center frequency |
-1000 |
- |
1000 |
ppm |
|
LO duty cycle |
LODC |
- |
45 |
- |
55 |
% |
|
Current consumption |
Icc |
- |
- |
3.0 |
5.0 |
mA |
|
Shutdown current |
Istd |
- |
- |
15 |
900 |
uA |
|
Reference signal - high level |
VRefH |
CMOS |
PLL_VDD-0.1 |
- |
PLL_VDD |
V |
|
Reference signal - low level |
VRefL |
0 |
- |
0.1 |
||
